www.pudn.com > project2.rar > cache_controller.v, change:2014-01-01,size:1849b


module	cache_controller
(clk,
reset,
ld,
st,
addr,
tag_loaded,
valid,
dirty,
l2_ack,
hit,
miss,
load_ready,
write_l1,
read_l2,
write_l2);

   input ld, st,clk,reset;
   input [31:0]addr;
   input [18:0]tag_loaded;
   input l2_ack,valid,dirty;
   output hit,miss;
   output load_ready,write_l1;
   output read_l2, write_l2;
   wire muxa0;
   wire muxb0;
   wire muxc0;
   wire muxaout;
   wire muxbout;
   wire muxcout;
   wire Q2;
   wire Q1;
   wire Q0;
   wire Done2;
   wire Done1;

   counter_n #(.N(3)) counter8(.clk(clk),.r(reset),.cin(Q2&(~Q1)&Q0),.cout(Done1),.q());
   counter_n #(.N(2)) counter4(.clk(clk),.r(l2_ack||reset),.cin(Q2&(~Q1)&(~Q0)),.cout(Done2),.q());
   
   assign compare=&(addr[31:13]~^tag_loaded[18:0]);
   assign muxa0=(ld && (~st) && (~compare) && valid && dirty) || (ld && (~st) && compare && valid) || ((~ld) && st && compare);
   assign muxb0=(~ld && st && ~compare) || (ld && ~st && compare && valid);
   assign muxc0=(ld && ~st && ~compare && valid && ~dirty) || (ld && ~st && ~valid) || (ld && ~st && ~compare && valid && dirty);
   

   mux8to1 muxa(.d0(muxa0),.d1(0),.d2(0),.d3(0),.d4(Done2),.d5(~Done1),.d6(0),.d7(0),.q(muxaout),.sel({Q2,Q1,Q0}));
   mux8to1 muxb(.d0(muxb0),.d1(0),.d2(0),.d3(0),.d4(Done2),.d5(0),.d6(0),.d7(0),.q(muxbout),.sel({Q2,Q1,Q0}));
   mux8to1 muxc(.d0(muxc0),.d1(0),.d2(0),.d3(0),.d4(~Done2),.d5(1),.d6(0),.d7(0),.q(muxcout),.sel({Q2,Q1,Q0}));

   dffr dffr0(.d(muxaout),.clk(clk),.r(reset),.q(Q0));
   dffr dffr1(.d(muxbout),.clk(clk),.r(reset),.q(Q1));
   dffr dffr2(.d(muxcout),.clk(clk),.r(reset),.q(Q2));

   assign hit=((~Q2)&Q1&Q0)|((~Q2)&(~Q1)&Q0);
   assign miss=((~Q2)&Q1&(~Q0))|(Q2&(~Q1));
   assign load_ready=(~Q2)&Q1&Q0;
   assign write_l1=((~Q2)&(~Q1)&Q0)|(Q2&(~Q1)&(~Q0));
   assign read_l2=Q2&(~Q1)&(~Q0);
   assign write_l2=((~Q2)&Q1&(~Q0))|(Q2&(~Q1)&Q0);

endmodule