www.pudn.com > project2.rar > _primary.vhd, change:2014-01-01,size:375b


library verilog;
use verilog.vl_types.all;
entity counter_n is
    generic(
        N               : integer := 4
    );
    port(
        q               : out    vl_logic_vector;
        cout            : out    vl_logic;
        cin             : in     vl_logic;
        r               : in     vl_logic;
        clk             : in     vl_logic
    );
end counter_n;