www.pudn.com > project2.rar > _primary.vhd, change:2014-01-01,size:793b


library verilog;
use verilog.vl_types.all;
entity cache_controller is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        ld              : in     vl_logic;
        st              : in     vl_logic;
        addr            : in     vl_logic_vector(31 downto 0);
        tag_loaded      : in     vl_logic_vector(18 downto 0);
        valid           : in     vl_logic;
        dirty           : in     vl_logic;
        l2_ack          : in     vl_logic;
        hit             : out    vl_logic;
        miss            : out    vl_logic;
        load_ready      : out    vl_logic;
        write_l1        : out    vl_logic;
        read_l2         : out    vl_logic;
        write_l2        : out    vl_logic
    );
end cache_controller;