www.pudn.com > project2.rar > voptv7t8it, change:2013-12-31,size:539b


library verilog;
use verilog.vl_types.all;
entity mux8to1 is
    port(
        d0              : in     vl_logic;
        d1              : in     vl_logic;
        d2              : in     vl_logic;
        d3              : in     vl_logic;
        d4              : in     vl_logic;
        d5              : in     vl_logic;
        d6              : in     vl_logic;
        d7              : in     vl_logic;
        q               : out    vl_logic;
        sel             : in     vl_logic_vector(2 downto 0)
    );
end mux8to1;