www.pudn.com > uda1380-s3c2410-linux-rev.zip.zip > uda1380.h
#define FMT_I2S 0 #define FMT_LSB16 1 #define FMT_LSB18 2 #define FMT_LSB20 3 #define FMT_MSB 5 #define REG0 0x00 #define REG0_EN_ADC (1 << 11) #define REG0_EN_DEC (1 << 10) #define REG0_EN_DAC (1 << 9) #define REG0_EN_INT (1 << 8) #define REG0_ADC_USE_WSPLL (1 << 5) #define REG0_ADC_USE_SYSCLK (0 << 5) #define REG0_DAC_USE_WSPLL (1 << 4) #define REG0_DAC_USE_SYSCLK (0 << 4) #define REG0_SC_MASK (3 << 2) #define REG0_SC_768FS (3 << 2) #define REG0_SC_512FS (2 << 2) #define REG0_SC_384FS (1 << 2) #define REG0_SC_256FS (0 << 2) #define REG0_PLL_MASK (3 << 0) #define REG0_PLL_6TO12 (0 << 0) #define REG0_PLL_12TO25 (1 << 0) #define REG0_PLL_25TO50 (2 << 0) #define REG0_PLL_50TO100 (3 << 0) #define I2S_REG 0x01 #define I2S_REG_SFORO_MASK (7 << 0) #define I2S_REG_SFORO_SHIFT 0 #define I2S_REG_SFORI_MASK (7 << 8) #define I2S_REG_SFORI_SHIFT 8 #define I2S_REG_SEL_DECIMATOR (1 << 6) #define I2S_REG_SEL_MIXER (1 << 6) #define I2S_REG_SIM_SLAVE (0 << 4) #define I2S_REG_SIM_MASTER (1 << 4) #define PWR_REG 0x02 #define PWR_REG_PON_PLL (1 << 15) #define PWR_REG_PON_HP (1 << 13) #define PWR_REG_PON_DAC (1 << 10) #define PWR_REG_PON_BIAS (1 << 8) #define PWR_REG_EN_AVC (1 << 7) #define PWR_REG_PON_AVC (1 << 6) #define PWR_REG_PON_LNA (1 << 4) #define PWR_REG_PON_PGAL (1 << 3) #define PWR_REG_PON_ADCL (1 << 2) #define PWR_REG_PON_PGAR (1 << 1) #define PWR_REG_PON_ADCR (1 << 0) /* analog mixer */ #define AMIX_REG 0x03 /* * the analog mixer enables line-input to be played on speaker or * headphones without running it through the digital section. * We do not use it on the iPAQ. * * iPAQ h3900: * - line-input is not connected * - built-in microphone connected to mic-in. No microphone jack. * - line-output mixed together at speaker amplifier. * - headphone amp goes to head-phone jack. earphone detect is on asic2. */ #define AMIX_AVCL(x) (((x) & 0x1f) << 8) #define AMIX_AVCL_MASK (0x1f << 8) #define AMIX_AVCR(x) (((x) & 0x1f) << 0) #define AMIX_AVCR_MASK (0x1f << 0) /* digital master volume control register */ #define MASTER_VOL_REG 0x10 #define MASTER_VCL(x) (((x) & 0xff) << 8) #define MASTER_VCL_MASK (0xff << 8) #define MASTER_VCR(x) (((x) & 0xff) << 0) #define MASTER_VCR_MASK (0xff << 0) /* digital mixer control register */ #define MIXER_VOL_REG 0x11 #define MIXER_VCL(x) (((x) & 0xff) << 8) #define MIXER_VCL_MASK (0xff << 8) #define MIXER_VCR(x) (((x) & 0xff) << 0) #define MIXER_VCR_MASK (0xff << 0) /* mode, bass boost, treble */ #define MBT_REG 0x12 #define MBT_MODE_MASK (3 << 14) #define MBT_MODE_FLAT (0 << 14) #define MBT_MODE_MIN (1 << 14) #define MBT_MODE_MAX (3 << 14) #define MBT_TRL_WIDTH 2 #define MBT_TRL_MASK (3 << 12) #define MBT_TRL(x) ((x) << 12) #define MBT_TRR_MASK (3 << 4) #define MBT_TRR(x) ((x) << 4) #define MBT_BBL_WIDTH 4 #define MBT_BBL_MASK (0xf << 8) #define MBT_BBL(x) ((x) << 8) #define MBT_BBR_MASK (0xf << 0) #define MBT_BBR(x) ((x) << 0) /* channel2 is from decimation filter */ /* channel1 is from digital data from I2S */ #define MMCDM_REG 0x13 #define MMCDM_MASTER_MUTE (1 << 14) #define MMCDM_CHANNEL2_MUTE (1 << 11) #define MMCDM_CHANNEL2_DEEMPHASIS_OFF (0 << 8) #define MMCDM_CHANNEL2_DEEMPHASIS_32KHZ (1 << 8) #define MMCDM_CHANNEL2_DEEMPHASIS_44KHZ (2 << 8) #define MMCDM_CHANNEL2_DEEMPHASIS_48KHZ (3 << 8) #define MMCDM_CHANNEL2_DEEMPHASIS_96KHZ (4 << 8) #define MMCDM_CHANNEL1_MUTE (1 << 3) #define MMCDM_CHANNEL1_DEEMPHASIS_32KHZ (1 << 8) #define MMCDM_CHANNEL1_DEEMPHASIS_44KHZ (2 << 8) #define MMCDM_CHANNEL1_DEEMPHASIS_48KHZ (3 << 8) #define MMCDM_CHANNEL1_DEEMPHASIS_96KHZ (4 << 8) #define MIXER_CTL_REG 0x14 #define MIXER_CTL_DAC_POLARITY_INVERT (1 << 15) #define MIXER_CTL_SEL_5TH_ORDER_NS (1 << 14) #define MIXER_CTL_MIX_POS (1 << 13) #define MIXER_CTL_MIX (1 << 12) #define MIXER_CTL_SILENCE (1 << 7) #define MIXER_CTL_SDET_ON (1 << 6) #define MIXER_CTL_SDET_VALUE_MASK (3 << 4) #define MIXER_CTL_SDET_VALUE_SHIFT 4 #define MIXER_CTL_OVERSAMPLING_MASK (3 << 0) #define MIXER_CTL_OVERSAMPLING_SHIFT 0 #define DEC_VOL_REG 0x20 #define DEC_VCL(x) (((x) & 0xff) << 8) #define DEC_VCL_MASK (0xff << 8) #define DEC_VCR(x) (((x) & 0xff) << 0) #define DEC_VCR_MASK (0xff << 0) #define DPM_REG 0x21 #define DPM_MUTE_ADC (1 << 15) #define DPM_GAINL(x) (((x) & 0xf) << 8) #define DPM_GAINL_MASK (0xf << 8) #define DPM_GAINR(x) (((x) & 0xf) << 0) #define DPM_GAINR_MASK (0xf << 0) #define DEC_ADC_REG 0x22 #define DEC_ADC_POL_INV (1 << 12) #define DEC_ADC_VGA_CTRL(x) ((x) << 8) #define DEC_ADC_VGA_CTRL_MASK (0xf << 8) #define DEC_ADC_SEL_LNA (1 << 3) #define DEC_ADC_SEL_MIC (1 << 2) #define DEC_ADC_SKIP_DCFIL (1 << 1) #define DEC_ADC_EN_DCFIL (1 << 0) #define DEC_AGC_REG 0x23 #define DEC_AGC_EN (1 << 0) #define REC_MASK (SOUND_MASK_LINE | SOUND_MASK_MIC) #define DEV_MASK (REC_MASK | SOUND_MASK_VOLUME | SOUND_MASK_BASS | SOUND_MASK_TREBLE)