www.pudn.com > UartLoop.rar > main_envsettings.html, change:2013-10-04,size:12383b


<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
 <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>LMC_HOME</td>
<td>d:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt</td>
<td>d:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt</td>
<td>d:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt</td>
<td>d:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt</td>
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH</td>
</tr>
<tr>
<td>Path</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>d:\Xilinx\12.4\ISE_DS\ISE\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\ISE\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\EDK\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\EDK\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\common\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\common\lib\nt;<br>d:\Xilinx\10.1\ISE\bin\nt;<br>d:\Xilinx\10.1\ISE\lib\nt;<br>d:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>D:\Program Files\Altium Designer Summer 09\System</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>d:\Xilinx\12.4\ISE_DS\ISE\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\ISE\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\EDK\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\EDK\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\common\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\common\lib\nt;<br>d:\Xilinx\10.1\ISE\bin\nt;<br>d:\Xilinx\10.1\ISE\lib\nt;<br>d:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>D:\Program Files\Altium Designer Summer 09\System</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>d:\Xilinx\12.4\ISE_DS\ISE\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\ISE\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\EDK\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\EDK\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\common\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\common\lib\nt;<br>d:\Xilinx\10.1\ISE\bin\nt;<br>d:\Xilinx\10.1\ISE\lib\nt;<br>d:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>D:\Program Files\Altium Designer Summer 09\System</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>d:\Xilinx\12.4\ISE_DS\ISE\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\ISE\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\EDK\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\EDK\lib\nt;<br>d:\Xilinx\12.4\ISE_DS\common\bin\nt;<br>d:\Xilinx\12.4\ISE_DS\common\lib\nt;<br>d:\Xilinx\10.1\ISE\bin\nt;<br>d:\Xilinx\10.1\ISE\lib\nt;<br>d:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>D:\Program Files\Altium Designer Summer 09\System</td>
</tr>
<tr>
<td>XILINX</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE\</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE\</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE\</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE\</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE</td>
<td>d:\Xilinx\12.4\ISE_DS\ISE</td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>d:\Xilinx\12.4\ISE_DS\EDK</td>
<td>d:\Xilinx\12.4\ISE_DS\EDK</td>
<td>d:\Xilinx\12.4\ISE_DS\EDK</td>
<td>d:\Xilinx\12.4\ISE_DS\EDK</td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>d:\Xilinx\12.4\ISE_DS\PlanAhead</td>
<td>d:\Xilinx\12.4\ISE_DS\PlanAhead</td>
<td>d:\Xilinx\12.4\ISE_DS\PlanAhead</td>
<td>d:\Xilinx\12.4\ISE_DS\PlanAhead</td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
 <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td> </td>
<td>main.prj</td>
<td> </td>
</tr>
<tr>
<td>-ifmt</td>
<td> </td>
<td>mixed</td>
<td>Mixed</td>
</tr>
<tr>
<td>-ofn</td>
<td> </td>
<td>main</td>
<td> </td>
</tr>
<tr>
<td>-ofmt</td>
<td> </td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td> </td>
<td>xc6slx9-3-tqg144</td>
<td> </td>
</tr>
<tr>
<td>-top</td>
<td> </td>
<td>main</td>
<td> </td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>Speed</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-power</td>
<td>Power Reduction</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>As_Optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>No</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>AllClockNets</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td><></td>
<td><></td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-dsp_utilization_ratio</td>
<td>DSP Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-reduce_control_sets</td>
<td> </td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td> </td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td> </td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td> </td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-fsm_style</td>
<td> </td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td> </td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-ram_style</td>
<td> </td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-rom_extract</td>
<td> </td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td> </td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-rom_style</td>
<td> </td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td> </td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td> </td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td> </td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_dsp48</td>
<td> </td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iobuf</td>
<td> </td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-max_fanout</td>
<td> </td>
<td>100000</td>
<td>100000</td>
</tr>
<tr>
<td>-bufg</td>
<td> </td>
<td>16</td>
<td>16</td>
</tr>
<tr>
<td>-register_duplication</td>
<td> </td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-register_balancing</td>
<td> </td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td> </td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td> </td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td> </td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td> </td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iob</td>
<td> </td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td> </td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td> </td>
<td>5</td>
<td>0</td>
</tr>
</TABLE>
<A NAME="Translation Property Settings"></A>
 <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td> </td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-dd</td>
<td> </td>
<td>_ngo</td>
<td>None</td>
</tr>
<tr>
<td>-p</td>
<td> </td>
<td>xc6slx9-tqg144-3</td>
<td>None</td>
</tr>
<tr>
<td>-uc</td>
<td> </td>
<td>F:/USB2.0/Tutorial_01/UartLoop/SRC/sp6-dp.ucf</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Map Property Settings"></A>
 <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>high</td>
</tr>
<tr>
<td>-xt</td>
<td>Extra Cost Tables</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>-ir</td>
<td>Use RLOC Constraints</td>
<td>OFF</td>
<td>OFF</td>
</tr>
<tr>
<td>-t</td>
<td>Starting Placer Cost Table (1-100) Map</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>-intstyle</td>
<td> </td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-lc</td>
<td>LUT Combining</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-o</td>
<td> </td>
<td>main_map.ncd</td>
<td>None</td>
</tr>
<tr>
<td>-w</td>
<td> </td>
<td>true</td>
<td>false</td>
</tr>
<tr>
<td>-pr</td>
<td>Pack I/O Registers/Latches into IOBs</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-p</td>
<td> </td>
<td>xc6slx9-tqg144-3</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Place and Route Property Settings"></A>
 <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td> </td>
<td>ise</td>
<td> </td>
</tr>
<tr>
<td>-mt</td>
<td>Enable Multi-Threading</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>std</td>
</tr>
<tr>
<td>-w</td>
<td> </td>
<td>true</td>
<td>false</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
 <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Pentium(R) Dual-Core  CPU      E5500  @ 2.80GHz/2800 MHz</td>
<td>Pentium(R) Dual-Core  CPU      E5500  @ 2.80GHz/2800 MHz</td>
<td>Pentium(R) Dual-Core  CPU      E5500  @ 2.80GHz/2800 MHz</td>
<td>Pentium(R) Dual-Core  CPU      E5500  @ 2.80GHz/2800 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>USER-20131002DF</td>
<td>USER-20131002DF</td>
<td>USER-20131002DF</td>
<td>USER-20131002DF</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 3  (build 2600)</td>
<td>Service Pack 3  (build 2600)</td>
<td>Service Pack 3  (build 2600)</td>
<td>Service Pack 3  (build 2600)</td>
</tr>
</TABLE>
</BODY> </HTML>