www.pudn.com > UartLoop.rar > main.twr, change:2013-10-02,size:30028b


-------------------------------------------------------------------------------- 
Release 12.4 Trace  (nt) 
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. 
 
d:\Xilinx\12.4\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n 
3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf 
 
Design file:              main.ncd 
Physical constraint file: main.pcf 
Device,package,speed:     xc6slx9,tqg144,C,-3 (PRELIMINARY 1.15 2010-12-02) 
Report level:             verbose report 
 
Environment Variable      Effect  
--------------------      ------  
NONE                      No environment variables were set 
-------------------------------------------------------------------------------- 
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths  
   option. All paths that are not constrained will be reported in the  
   unconstrained paths section(s) of the report. 
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on  
   a 50 Ohm transmission line loading model.  For the details of this model,  
   and for more information on accounting for different loading conditions,  
   please see the device datasheet. 
 
================================================================================ 
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH 50%; 
 
 739 paths analyzed, 294 endpoints analyzed, 0 failing endpoints 
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) 
 Minimum period is   3.522ns. 
-------------------------------------------------------------------------------- 
 
Paths for end point U2/Dsin_8 (SLICE_X4Y17.A4), 4 paths 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.478ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               U2/C2_0 (FF) 
  Destination:          U2/Dsin_8 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.475ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.012ns (0.281 - 0.293) 
  Source Clock:         Clk_BUFGP rising at 0.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: U2/C2_0 to U2/Dsin_8 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y18.AQ       Tcko                  0.391   U2/C2<2> 
                                                       U2/C2_0 
    SLICE_X7Y18.D2       net (fanout=7)        0.611   U2/C2<0> 
    SLICE_X7Y18.D        Tilo                  0.259   U2/C2<2> 
                                                       U2/Msub_C2[2]_GND_3_o_sub_16_OUT_xor<1>11 
    SLICE_X4Y18.B3       net (fanout=4)        1.286   U2/C2[2]_GND_3_o_sub_16_OUT<1> 
    SLICE_X4Y18.B        Tilo                  0.203   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0> 
                                                       U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_7_0 
    SLICE_X4Y17.A4       net (fanout=1)        0.436   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<7> 
    SLICE_X4Y17.CLK      Tas                   0.289   U2/Dsin<8> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT81 
                                                       U2/Dsin_8 
    -------------------------------------------------  --------------------------- 
    Total                                      3.475ns (1.142ns logic, 2.333ns route) 
                                                       (32.9% logic, 67.1% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.836ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               U2/C2_1 (FF) 
  Destination:          U2/Dsin_8 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.117ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.012ns (0.281 - 0.293) 
  Source Clock:         Clk_BUFGP rising at 0.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: U2/C2_1 to U2/Dsin_8 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y18.BQ       Tcko                  0.391   U2/C2<2> 
                                                       U2/C2_1 
    SLICE_X7Y18.D4       net (fanout=6)        0.253   U2/C2<1> 
    SLICE_X7Y18.D        Tilo                  0.259   U2/C2<2> 
                                                       U2/Msub_C2[2]_GND_3_o_sub_16_OUT_xor<1>11 
    SLICE_X4Y18.B3       net (fanout=4)        1.286   U2/C2[2]_GND_3_o_sub_16_OUT<1> 
    SLICE_X4Y18.B        Tilo                  0.203   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0> 
                                                       U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_7_0 
    SLICE_X4Y17.A4       net (fanout=1)        0.436   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<7> 
    SLICE_X4Y17.CLK      Tas                   0.289   U2/Dsin<8> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT81 
                                                       U2/Dsin_8 
    -------------------------------------------------  --------------------------- 
    Total                                      3.117ns (1.142ns logic, 1.975ns route) 
                                                       (36.6% logic, 63.4% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     17.475ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               U2/C2_0 (FF) 
  Destination:          U2/Dsin_8 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      2.478ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.012ns (0.281 - 0.293) 
  Source Clock:         Clk_BUFGP rising at 0.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: U2/C2_0 to U2/Dsin_8 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y18.AQ       Tcko                  0.391   U2/C2<2> 
                                                       U2/C2_0 
    SLICE_X7Y18.A6       net (fanout=7)        0.136   U2/C2<0> 
    SLICE_X7Y18.A        Tilo                  0.259   U2/C2<2> 
                                                       U2/s[0]_C2[2]_wide_mux_25_OUT<0>1_INV_0 
    SLICE_X4Y18.B2       net (fanout=4)        0.764   U2/s[0]_C2[2]_wide_mux_25_OUT<0> 
    SLICE_X4Y18.B        Tilo                  0.203   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0> 
                                                       U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_7_0 
    SLICE_X4Y17.A4       net (fanout=1)        0.436   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<7> 
    SLICE_X4Y17.CLK      Tas                   0.289   U2/Dsin<8> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT81 
                                                       U2/Dsin_8 
    -------------------------------------------------  --------------------------- 
    Total                                      2.478ns (1.142ns logic, 1.336ns route) 
                                                       (46.1% logic, 53.9% route) 
 
-------------------------------------------------------------------------------- 
 
Paths for end point U2/Dsin_5 (SLICE_X5Y18.B3), 4 paths 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.495ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               U2/C2_0 (FF) 
  Destination:          U2/Dsin_5 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.457ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.013ns (0.280 - 0.293) 
  Source Clock:         Clk_BUFGP rising at 0.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: U2/C2_0 to U2/Dsin_5 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y18.AQ       Tcko                  0.391   U2/C2<2> 
                                                       U2/C2_0 
    SLICE_X7Y18.D2       net (fanout=7)        0.611   U2/C2<0> 
    SLICE_X7Y18.D        Tilo                  0.259   U2/C2<2> 
                                                       U2/Msub_C2[2]_GND_3_o_sub_16_OUT_xor<1>11 
    SLICE_X4Y18.B3       net (fanout=4)        1.286   U2/C2[2]_GND_3_o_sub_16_OUT<1> 
    SLICE_X4Y18.BMUX     Tilo                  0.261   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0> 
                                                       U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_4_0 
    SLICE_X5Y18.B3       net (fanout=1)        0.327   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<4> 
    SLICE_X5Y18.CLK      Tas                   0.322   U2/Dsin<7> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT51 
                                                       U2/Dsin_5 
    -------------------------------------------------  --------------------------- 
    Total                                      3.457ns (1.233ns logic, 2.224ns route) 
                                                       (35.7% logic, 64.3% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.853ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               U2/C2_1 (FF) 
  Destination:          U2/Dsin_5 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.099ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.013ns (0.280 - 0.293) 
  Source Clock:         Clk_BUFGP rising at 0.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: U2/C2_1 to U2/Dsin_5 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y18.BQ       Tcko                  0.391   U2/C2<2> 
                                                       U2/C2_1 
    SLICE_X7Y18.D4       net (fanout=6)        0.253   U2/C2<1> 
    SLICE_X7Y18.D        Tilo                  0.259   U2/C2<2> 
                                                       U2/Msub_C2[2]_GND_3_o_sub_16_OUT_xor<1>11 
    SLICE_X4Y18.B3       net (fanout=4)        1.286   U2/C2[2]_GND_3_o_sub_16_OUT<1> 
    SLICE_X4Y18.BMUX     Tilo                  0.261   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0> 
                                                       U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_4_0 
    SLICE_X5Y18.B3       net (fanout=1)        0.327   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<4> 
    SLICE_X5Y18.CLK      Tas                   0.322   U2/Dsin<7> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT51 
                                                       U2/Dsin_5 
    -------------------------------------------------  --------------------------- 
    Total                                      3.099ns (1.233ns logic, 1.866ns route) 
                                                       (39.8% logic, 60.2% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     17.492ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               U2/C2_0 (FF) 
  Destination:          U2/Dsin_5 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      2.460ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.013ns (0.280 - 0.293) 
  Source Clock:         Clk_BUFGP rising at 0.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: U2/C2_0 to U2/Dsin_5 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y18.AQ       Tcko                  0.391   U2/C2<2> 
                                                       U2/C2_0 
    SLICE_X7Y18.A6       net (fanout=7)        0.136   U2/C2<0> 
    SLICE_X7Y18.A        Tilo                  0.259   U2/C2<2> 
                                                       U2/s[0]_C2[2]_wide_mux_25_OUT<0>1_INV_0 
    SLICE_X4Y18.B2       net (fanout=4)        0.764   U2/s[0]_C2[2]_wide_mux_25_OUT<0> 
    SLICE_X4Y18.BMUX     Tilo                  0.261   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0> 
                                                       U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_4_0 
    SLICE_X5Y18.B3       net (fanout=1)        0.327   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<4> 
    SLICE_X5Y18.CLK      Tas                   0.322   U2/Dsin<7> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT51 
                                                       U2/Dsin_5 
    -------------------------------------------------  --------------------------- 
    Total                                      2.460ns (1.233ns logic, 1.227ns route) 
                                                       (50.1% logic, 49.9% route) 
 
-------------------------------------------------------------------------------- 
 
Paths for end point U2/Dsin_7 (SLICE_X5Y18.D2), 4 paths 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.840ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               U2/C2_0 (FF) 
  Destination:          U2/Dsin_7 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.112ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.013ns (0.280 - 0.293) 
  Source Clock:         Clk_BUFGP rising at 0.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: U2/C2_0 to U2/Dsin_7 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y18.AQ       Tcko                  0.391   U2/C2<2> 
                                                       U2/C2_0 
    SLICE_X7Y18.D2       net (fanout=7)        0.611   U2/C2<0> 
    SLICE_X7Y18.D        Tilo                  0.259   U2/C2<2> 
                                                       U2/Msub_C2[2]_GND_3_o_sub_16_OUT_xor<1>11 
    SLICE_X4Y18.A3       net (fanout=4)        0.733   U2/C2[2]_GND_3_o_sub_16_OUT<1> 
    SLICE_X4Y18.A        Tilo                  0.203   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0> 
                                                       U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_6_0 
    SLICE_X5Y18.D2       net (fanout=1)        0.593   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<6> 
    SLICE_X5Y18.CLK      Tas                   0.322   U2/Dsin<7> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT71 
                                                       U2/Dsin_7 
    -------------------------------------------------  --------------------------- 
    Total                                      3.112ns (1.175ns logic, 1.937ns route) 
                                                       (37.8% logic, 62.2% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     17.198ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               U2/C2_1 (FF) 
  Destination:          U2/Dsin_7 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      2.754ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.013ns (0.280 - 0.293) 
  Source Clock:         Clk_BUFGP rising at 0.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: U2/C2_1 to U2/Dsin_7 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y18.BQ       Tcko                  0.391   U2/C2<2> 
                                                       U2/C2_1 
    SLICE_X7Y18.D4       net (fanout=6)        0.253   U2/C2<1> 
    SLICE_X7Y18.D        Tilo                  0.259   U2/C2<2> 
                                                       U2/Msub_C2[2]_GND_3_o_sub_16_OUT_xor<1>11 
    SLICE_X4Y18.A3       net (fanout=4)        0.733   U2/C2[2]_GND_3_o_sub_16_OUT<1> 
    SLICE_X4Y18.A        Tilo                  0.203   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0> 
                                                       U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_6_0 
    SLICE_X5Y18.D2       net (fanout=1)        0.593   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<6> 
    SLICE_X5Y18.CLK      Tas                   0.322   U2/Dsin<7> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT71 
                                                       U2/Dsin_7 
    -------------------------------------------------  --------------------------- 
    Total                                      2.754ns (1.175ns logic, 1.579ns route) 
                                                       (42.7% logic, 57.3% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     17.412ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               U2/C2_0 (FF) 
  Destination:          U2/Dsin_7 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      2.540ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.013ns (0.280 - 0.293) 
  Source Clock:         Clk_BUFGP rising at 0.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: U2/C2_0 to U2/Dsin_7 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y18.AQ       Tcko                  0.391   U2/C2<2> 
                                                       U2/C2_0 
    SLICE_X7Y18.A6       net (fanout=7)        0.136   U2/C2<0> 
    SLICE_X7Y18.A        Tilo                  0.259   U2/C2<2> 
                                                       U2/s[0]_C2[2]_wide_mux_25_OUT<0>1_INV_0 
    SLICE_X4Y18.A2       net (fanout=4)        0.636   U2/s[0]_C2[2]_wide_mux_25_OUT<0> 
    SLICE_X4Y18.A        Tilo                  0.203   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0> 
                                                       U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_6_0 
    SLICE_X5Y18.D2       net (fanout=1)        0.593   U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<6> 
    SLICE_X5Y18.CLK      Tas                   0.322   U2/Dsin<7> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT71 
                                                       U2/Dsin_7 
    -------------------------------------------------  --------------------------- 
    Total                                      2.540ns (1.175ns logic, 1.365ns route) 
                                                       (46.3% logic, 53.7% route) 
 
-------------------------------------------------------------------------------- 
 
Hold Paths: TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH 50%; 
-------------------------------------------------------------------------------- 
 
Paths for end point U2/Dsin_1 (SLICE_X6Y17.A6), 1 path 
-------------------------------------------------------------------------------- 
Slack (hold path):      0.412ns (requirement - (clock path skew + uncertainty - data path)) 
  Source:               U2/Dsin_1 (FF) 
  Destination:          U2/Dsin_1 (FF) 
  Requirement:          0.000ns 
  Data Path Delay:      0.412ns (Levels of Logic = 1) 
  Clock Path Skew:      0.000ns 
  Source Clock:         Clk_BUFGP rising at 20.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.000ns 
 
  Minimum Data Path at Fast Process Corner: U2/Dsin_1 to U2/Dsin_1 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X6Y17.AQ       Tcko                  0.200   U2/Dsin<3> 
                                                       U2/Dsin_1 
    SLICE_X6Y17.A6       net (fanout=2)        0.022   U2/Dsin<1> 
    SLICE_X6Y17.CLK      Tah         (-Th)    -0.190   U2/Dsin<3> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT11 
                                                       U2/Dsin_1 
    -------------------------------------------------  --------------------------- 
    Total                                      0.412ns (0.390ns logic, 0.022ns route) 
                                                       (94.7% logic, 5.3% route) 
 
-------------------------------------------------------------------------------- 
 
Paths for end point U2/Dsin_3 (SLICE_X6Y17.D6), 1 path 
-------------------------------------------------------------------------------- 
Slack (hold path):      0.416ns (requirement - (clock path skew + uncertainty - data path)) 
  Source:               U2/Dsin_3 (FF) 
  Destination:          U2/Dsin_3 (FF) 
  Requirement:          0.000ns 
  Data Path Delay:      0.416ns (Levels of Logic = 1) 
  Clock Path Skew:      0.000ns 
  Source Clock:         Clk_BUFGP rising at 20.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.000ns 
 
  Minimum Data Path at Fast Process Corner: U2/Dsin_3 to U2/Dsin_3 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X6Y17.DQ       Tcko                  0.200   U2/Dsin<3> 
                                                       U2/Dsin_3 
    SLICE_X6Y17.D6       net (fanout=2)        0.026   U2/Dsin<3> 
    SLICE_X6Y17.CLK      Tah         (-Th)    -0.190   U2/Dsin<3> 
                                                       U2/Mmux_PWR_4_o_PWR_4_o_mux_16_OUT31 
                                                       U2/Dsin_3 
    -------------------------------------------------  --------------------------- 
    Total                                      0.416ns (0.390ns logic, 0.026ns route) 
                                                       (93.8% logic, 6.3% route) 
 
-------------------------------------------------------------------------------- 
 
Paths for end point U1/Dout_0 (SLICE_X2Y18.A6), 1 path 
-------------------------------------------------------------------------------- 
Slack (hold path):      0.422ns (requirement - (clock path skew + uncertainty - data path)) 
  Source:               U1/Dout_0 (FF) 
  Destination:          U1/Dout_0 (FF) 
  Requirement:          0.000ns 
  Data Path Delay:      0.422ns (Levels of Logic = 1) 
  Clock Path Skew:      0.000ns 
  Source Clock:         Clk_BUFGP rising at 20.000ns 
  Destination Clock:    Clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.000ns 
 
  Minimum Data Path at Fast Process Corner: U1/Dout_0 to U1/Dout_0 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X2Y18.AQ       Tcko                  0.200   U1/Dout<1> 
                                                       U1/Dout_0 
    SLICE_X2Y18.A6       net (fanout=3)        0.032   U1/Dout<0> 
    SLICE_X2Y18.CLK      Tah         (-Th)    -0.190   U1/Dout<1> 
                                                       U1/Dout_0_dpot 
                                                       U1/Dout_0 
    -------------------------------------------------  --------------------------- 
    Total                                      0.422ns (0.390ns logic, 0.032ns route) 
                                                       (92.4% logic, 7.6% route) 
 
-------------------------------------------------------------------------------- 
 
Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH 50%; 
-------------------------------------------------------------------------------- 
Slack: 18.270ns (period - min period limit) 
  Period: 20.000ns 
  Min period limit: 1.730ns (578.035MHz) (Tbcper_I) 
  Physical resource: Clk_BUFGP/BUFG/I0 
  Logical resource: Clk_BUFGP/BUFG/I0 
  Location pin: BUFGMUX_X3Y8.I0 
  Clock network: Clk_BUFGP/IBUFG 
-------------------------------------------------------------------------------- 
Slack: 19.000ns (period - min period limit) 
  Period: 20.000ns 
  Min period limit: 1.000ns (1000.000MHz) (Tcp) 
  Physical resource: U1/RxdD2/CLK 
  Logical resource: U1/Mshreg_RxdD2/CLK 
  Location pin: SLICE_X0Y12.CLK 
  Clock network: Clk_BUFGP 
-------------------------------------------------------------------------------- 
Slack: 19.000ns (period - min period limit) 
  Period: 20.000ns 
  Min period limit: 1.000ns (1000.000MHz) (Tcp) 
  Physical resource: U2/C2[2]_DBin[3][7]_wide_mux_14_OUT<0>/CLK 
  Logical resource: U2/Mshreg_C2[2]_DBin[3][7]_wide_mux_14_OUT_5_0/CLK 
  Location pin: SLICE_X4Y18.CLK 
  Clock network: Clk_BUFGP 
-------------------------------------------------------------------------------- 
 
 
All constraints were met. 
 
 
Data Sheet report: 
----------------- 
All values displayed in nanoseconds (ns) 
 
Clock to Setup on destination clock Clk 
---------------+---------+---------+---------+---------+ 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall| 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| 
---------------+---------+---------+---------+---------+ 
Clk            |    3.522|         |         |         | 
---------------+---------+---------+---------+---------+ 
 
 
Timing summary: 
--------------- 
 
Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0) 
 
Constraints cover 739 paths, 0 nets, and 428 connections 
 
Design statistics: 
   Minimum period:   3.522ns{1}   (Maximum frequency: 283.930MHz) 
 
 
------------------------------------Footnotes----------------------------------- 
1)  The minimum period statistic assumes all single cycle delays. 
 
Analysis completed Wed Oct 02 21:30:14 2013  
-------------------------------------------------------------------------------- 
 
Trace Settings: 
------------------------- 
Trace Settings  
 
Peak Memory Usage: 121 MB