www.pudn.com > UartLoop.rar > main.syr, change:2013-10-02,size:23133b


Release 12.4 - xst M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.25 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.25 secs
 
--> Reading design: main.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "main.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "main"
Output Format                      : NGC
Target Device                      : xc6slx9-3-tqg144

---- Source Options
Top Module Name                    : main
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file \"\USB2.0\Tutorial_01\UartLoop\UartLoop\../SRC/UartTxd.v\" into library work
Parsing module <UartTxd>.
Analyzing Verilog file \"\USB2.0\Tutorial_01\UartLoop\UartLoop\../SRC/UartRxd.v\" into library work
Parsing module <UartRxd>.
Analyzing Verilog file \"\USB2.0\Tutorial_01\UartLoop\UartLoop\../SRC/main.v\" into library work
Parsing module <main>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <main>.

Elaborating module <UartRxd>.
WARNING:HDLCompiler:413 - "\USB2.0\Tutorial_01\UartLoop\UartLoop\../SRC/UartRxd.v" Line 50: Result of 5-bit expression is truncated to fit in 4-bit target.

Elaborating module <UartTxd>.
WARNING:HDLCompiler:1127 - "\USB2.0\Tutorial_01\UartLoop\UartLoop\../SRC/main.v" Line 18: Assignment to IsTxdDone ignored, since the identifier is never used

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <main>.
    Related source file is "/usb2.0/tutorial_01/uartloop/src/main.v".
INFO:Xst:3010 - "/usb2.0/tutorial_01/uartloop/src/main.v" line 18: Output port <IsDone> of the instance <U2> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <main> synthesized.

Synthesizing Unit <UartRxd>.
    Related source file is "/usb2.0/tutorial_01/uartloop/src/uartrxd.v".
        IDLE = 1'b0
        SAMP = 1'b1
    Found 7-bit register for signal <C1>.
    Found 1-bit register for signal <RxdD1>.
    Found 1-bit register for signal <RxdD2>.
    Found 1-bit register for signal <IsDone>.
    Found 4-bit register for signal <C2>.
    Found 4-bit register for signal <C3>.
    Found 1-bit register for signal <s>.
    Found 4-bit register for signal <i>.
    Found 1-bit register for signal <IsSta>.
    Found 8-bit register for signal <Dout>.
    Found 1-bit register for signal <Clk16>.
    Found 7-bit adder for signal <C1[6]_GND_2_o_add_2_OUT> created at line 20.
    Found 4-bit adder for signal <C2[3]_GND_2_o_add_8_OUT> created at line 49.
    Found 4-bit adder for signal <C3[3]_GND_2_o_add_9_OUT> created at line 50.
    Found 4-bit adder for signal <i[3]_GND_2_o_add_22_OUT> created at line 61.
    Found 7-bit comparator greater for signal <C1[6]_PWR_2_o_LessThan_2_o> created at line 20
    Found 4-bit comparator greater for signal <C2[3]_PWR_2_o_LessThan_8_o> created at line 48
    Found 4-bit comparator greater for signal <C3[3]_GND_2_o_LessThan_14_o> created at line 52
    Found 4-bit comparator lessequal for signal <i[3]_PWR_2_o_LessThan_16_o> created at line 60
    Found 4-bit comparator greater for signal <GND_2_o_C3[3]_LessThan_17_o> created at line 61
    Found 4-bit comparator lessequal for signal <n0032> created at line 61
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  33 D-type flip-flop(s).
	inferred   6 Comparator(s).
	inferred  19 Multiplexer(s).
Unit <UartRxd> synthesized.

Synthesizing Unit <UartTxd>.
    Related source file is "/usb2.0/tutorial_01/uartloop/src/uarttxd.v".
        IDLE = 1'b0
        SEND = 1'b1
    Found 11-bit register for signal <C1>.
    Found 1-bit register for signal <IsSta1>.
    Found 1-bit register for signal <IsSta2>.
    Found 32-bit register for signal <n0049[31:0]>.
    Found 3-bit register for signal <C2>.
    Found 1-bit register for signal <IsDone>.
    Found 1-bit register for signal <Txd>.
    Found 4-bit register for signal <i>.
    Found 1-bit register for signal <s>.
    Found 1-bit register for signal <ClkEn>.
    Found 10-bit register for signal <Dsin>.
    Found 1-bit register for signal <Clkt>.
    Found 3-bit subtractor for signal <C2[2]_GND_3_o_sub_16_OUT> created at line 61.
    Found 11-bit adder for signal <C1[10]_GND_3_o_add_2_OUT> created at line 21.
    Found 3-bit adder for signal <C2[2]_GND_3_o_add_8_OUT> created at line 52.
    Found 4-bit adder for signal <i[3]_GND_3_o_add_20_OUT> created at line 65.
    Found 8-bit 4-to-1 multiplexer for signal <C2[2]_DBin[3][7]_wide_mux_14_OUT> created at line 61.
    Found 1-bit 10-to-1 multiplexer for signal <i[3]_X_3_o_Mux_19_o> created at line 65.
    Found 11-bit comparator greater for signal <C1[10]_PWR_4_o_LessThan_2_o> created at line 21
    Found 3-bit comparator greater for signal <C2[2]_GND_3_o_LessThan_12_o> created at line 55
    Found 3-bit comparator greater for signal <GND_3_o_C2[2]_LessThan_13_o> created at line 61
    Found 4-bit comparator lessequal for signal <i[3]_PWR_4_o_LessThan_19_o> created at line 65
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  67 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred   5 Multiplexer(s).
Unit <UartTxd> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 8
 11-bit adder                                          : 1
 3-bit adder                                           : 1
 3-bit subtractor                                      : 1
 4-bit adder                                           : 4
 7-bit adder                                           : 1
# Registers                                            : 23
 1-bit register                                        : 13
 10-bit register                                       : 1
 11-bit register                                       : 1
 3-bit register                                        : 1
 32-bit register                                       : 1
 4-bit register                                        : 4
 7-bit register                                        : 1
 8-bit register                                        : 1
# Comparators                                          : 10
 11-bit comparator greater                             : 1
 3-bit comparator greater                              : 2
 4-bit comparator greater                              : 3
 4-bit comparator lessequal                            : 3
 7-bit comparator greater                              : 1
# Multiplexers                                         : 24
 1-bit 10-to-1 multiplexer                             : 1
 1-bit 2-to-1 multiplexer                              : 18
 10-bit 2-to-1 multiplexer                             : 1
 3-bit 2-to-1 multiplexer                              : 2
 8-bit 2-to-1 multiplexer                              : 1
 8-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <UartRxd>.
The following registers are absorbed into counter <C1>: 1 register on signal <C1>.
The following registers are absorbed into counter <C2>: 1 register on signal <C2>.
The following registers are absorbed into counter <C3>: 1 register on signal <C3>.
The following registers are absorbed into counter <i>: 1 register on signal <i>.
Unit <UartRxd> synthesized (advanced).

Synthesizing (advanced) Unit <UartTxd>.
The following registers are absorbed into counter <C1>: 1 register on signal <C1>.
The following registers are absorbed into counter <i>: 1 register on signal <i>.
Unit <UartTxd> synthesized (advanced).

Synthesizing (advanced) Unit <UartTxd>.
	Found 4-bit dynamic shift register for signal <C2[2]_DBin[3][7]_wide_mux_14_OUT<0>>.
	Found 4-bit dynamic shift register for signal <C2[2]_DBin[3][7]_wide_mux_14_OUT<1>>.
	Found 4-bit dynamic shift register for signal <C2[2]_DBin[3][7]_wide_mux_14_OUT<2>>.
	Found 4-bit dynamic shift register for signal <C2[2]_DBin[3][7]_wide_mux_14_OUT<3>>.
	Found 4-bit dynamic shift register for signal <C2[2]_DBin[3][7]_wide_mux_14_OUT<4>>.
	Found 4-bit dynamic shift register for signal <C2[2]_DBin[3][7]_wide_mux_14_OUT<5>>.
	Found 4-bit dynamic shift register for signal <C2[2]_DBin[3][7]_wide_mux_14_OUT<6>>.
	Found 4-bit dynamic shift register for signal <C2[2]_DBin[3][7]_wide_mux_14_OUT<7>>.
Unit <UartTxd> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 3-bit adder                                           : 1
 3-bit subtractor                                      : 1
# Counters                                             : 6
 11-bit up counter                                     : 1
 4-bit up counter                                      : 4
 7-bit up counter                                      : 1
# Registers                                            : 34
 Flip-Flops                                            : 34
# Shift Registers                                      : 8
 4-bit dynamic shift register                          : 8
# Comparators                                          : 10
 11-bit comparator greater                             : 1
 3-bit comparator greater                              : 2
 4-bit comparator greater                              : 3
 4-bit comparator lessequal                            : 3
 7-bit comparator greater                              : 1
# Multiplexers                                         : 23
 1-bit 10-to-1 multiplexer                             : 1
 1-bit 2-to-1 multiplexer                              : 18
 10-bit 2-to-1 multiplexer                             : 1
 3-bit 2-to-1 multiplexer                              : 2
 8-bit 2-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <Dsin_0> (without init value) has a constant value of 0 in block <UartTxd>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Dsin_9> (without init value) has a constant value of 1 in block <UartTxd>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <main> ...

Optimizing unit <UartRxd> ...

Optimizing unit <UartTxd> ...
WARNING:Xst:2677 - Node <U2/IsDone> of sequential type is unconnected in block <main>.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 2.

Final Macro Processing ...

Processing Unit <main> :
	Found 2-bit shift register for signal <U1/RxdD2>.
Unit <main> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 63
 Flip-Flops                                            : 63
# Shift Registers                                      : 1
 2-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : main.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 127
#      GND                         : 1
#      INV                         : 5
#      LUT1                        : 10
#      LUT2                        : 17
#      LUT3                        : 16
#      LUT4                        : 8
#      LUT5                        : 19
#      LUT6                        : 29
#      MUXCY                       : 10
#      VCC                         : 1
#      XORCY                       : 11
# FlipFlops/Latches                : 64
#      FD                          : 31
#      FDE                         : 21
#      FDR                         : 7
#      FDRE                        : 4
#      FDSE                        : 1
# Shift Registers                  : 9
#      SRLC16E                     : 9
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 2
#      IBUF                        : 1
#      OBUF                        : 1

Device utilization summary:
---------------------------

Selected Device : 6slx9tqg144-3 


Slice Logic Utilization: 
 Number of Slice Registers:              64  out of  11440     0%  
 Number of Slice LUTs:                  113  out of   5720     1%  
    Number used as Logic:               104  out of   5720     1%  
    Number used as Memory:                9  out of   1440     0%  
       Number used as SRL:                9

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    115
   Number with an unused Flip Flop:      51  out of    115    44%  
   Number with an unused LUT:             2  out of    115     1%  
   Number of fully used LUT-FF pairs:    62  out of    115    53%  
   Number of unique control sets:         7

IO Utilization: 
 Number of IOs:                           3
 Number of bonded IOBs:                   3  out of    102     2%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk                                | BUFGP                  | 73    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 3.631ns (Maximum Frequency: 275.372MHz)
   Minimum input arrival time before clock: 1.801ns
   Maximum output required time after clock: 3.597ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'Clk'
  Clock period: 3.631ns (frequency: 275.372MHz)
  Total number of paths / destination ports: 764 / 133
-------------------------------------------------------------------------
Delay:               3.631ns (Levels of Logic = 3)
  Source:            U2/C1_4 (FF)
  Destination:       U2/C1_10 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising

  Data Path: U2/C1_4 to U2/C1_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.447   0.961  U2/C1_4 (U2/C1_4)
     LUT5:I0->O            3   0.203   0.651  U2/Mcount_C1_val21 (U2/Mcount_C1_val2)
     LUT6:I5->O           10   0.205   0.857  U2/Mcount_C1_val1 (U2/Mcount_C1_val)
     LUT2:I1->O            1   0.205   0.000  U2/C1_10_rstpot (U2/C1_10_rstpot)
     FD:D                      0.102          U2/C1_10
    ----------------------------------------
    Total                      3.631ns (1.162ns logic, 2.469ns route)
                                       (32.0% logic, 68.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              1.801ns (Levels of Logic = 1)
  Source:            Rxd (PAD)
  Destination:       U1/Mshreg_RxdD2 (FF)
  Destination Clock: Clk rising

  Data Path: Rxd to U1/Mshreg_RxdD2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.579  Rxd_IBUF (Rxd_IBUF)
     SRLC16E:D                -0.060          U1/Mshreg_RxdD2
    ----------------------------------------
    Total                      1.801ns (1.222ns logic, 0.579ns route)
                                       (67.9% logic, 32.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.597ns (Levels of Logic = 1)
  Source:            U2/Txd (FF)
  Destination:       Txd (PAD)
  Source Clock:      Clk rising

  Data Path: U2/Txd to Txd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDSE:C->Q             1   0.447   0.579  U2/Txd (U2/Txd)
     OBUF:I->O                 2.571          Txd_OBUF (Txd)
    ----------------------------------------
    Total                      3.597ns (3.018ns logic, 0.579ns route)
                                       (83.9% logic, 16.1% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock Clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Clk            |    3.631|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.30 secs
 
--> 

Total memory usage is 146924 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    1 (   0 filtered)