www.pudn.com > UartLoop.rar > main.par, change:2013-10-02,size:8030b


Release 12.4 par M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

USER-20131002DF::  Wed Oct 02 21:29:51 2013

par -w -intstyle ise -ol high -mt off main_map.ncd main.ncd main.pcf 


Constraints file: main.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment d:\Xilinx\12.4\ISE_DS\ISE\.
   "main" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRELIMINARY 1.15 2010-12-02".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                    64 out of  11,440    1%
    Number used as Flip Flops:                  64
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                         98 out of   5,720    1%
    Number used as logic:                       92 out of   5,720    1%
      Number using O6 output only:              71
      Number using O5 output only:               9
      Number using O5 and O6:                   12
      Number used as ROM:                        0
    Number used as Memory:                       5 out of   1,440    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             5
        Number using O6 output only:             1
        Number using O5 output only:             0
        Number using O5 and O6:                  4
    Number used exclusively as route-thrus:      1
      Number with same-slice register load:      0
      Number with same-slice carry load:         1
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                    30 out of   1,430    2%
  Number of LUT Flip Flop pairs used:           99
    Number with an unused Flip Flop:            39 out of      99   39%
    Number with an unused LUT:                   1 out of      99    1%
    Number of fully used LUT-FF pairs:          59 out of      99   59%
    Number of slice register sites lost
      to control set restrictions:               0 out of  11,440    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         3 out of     102    2%
    Number of LOCed IOBs:                        3 out of       3  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
    Number used as BUFGs:                        1
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 8 secs 
Finished initial Timing Analysis.  REAL time: 8 secs 

Starting Router


Phase  1  : 474 unrouted;      REAL time: 8 secs 

Phase  2  : 407 unrouted;      REAL time: 9 secs 

Phase  3  : 132 unrouted;      REAL time: 9 secs 

Phase  4  : 132 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 10 secs 

Updating file: main.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 11 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 11 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 11 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 11 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 11 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 11 secs 
Total REAL time to Router completion: 11 secs 
Total CPU time to Router completion: 10 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           Clk_BUFGP |  BUFGMUX_X3Y8| No   |   25 |  0.086     |  1.183      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH  | SETUP       |    16.478ns|     3.522ns|       0|           0
  50%                                       | HOLD        |     0.412ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 11 secs 
Total CPU time to PAR completion: 11 secs 

Peak Memory Usage:  168 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file main.ncd



PAR done!