www.pudn.com > UartLoop.rar > sp6-dp.ucf, change:2013-10-02,size:231b



NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50 %;

NET "clk" 			 LOC = P123	| IOSTANDARD = LVCMOS33; 

NET "txd" 			 LOC = P38  | IOSTANDARD  = LVTTL;
NET "rxd" 			 LOC = P39  | IOSTANDARD  = LVTTL;