www.pudn.com > UartLoop.rar > UartTxd.v, change:2013-07-04,size:1565b


/****************************************************************************** 
designer :openpuu.com 
data	   :2013.5.10 
version  :1.1 
name     :uart trainsmiter
******************************************************************************/
`timescale 1 ns / 1 ns
module UartTxd (Clk,IsSta,Din,IsDone,Txd);

input Clk;
input IsSta;
input [7:0] Din;
output IsDone;
output Txd;

reg [10:0] C1;
reg ClkEn;
reg Clkt;
always @ (posedge	Clk )  //1倍波特率发生器,波特率为38400;系统时钟50MHZ,分频系数1302
	if( ClkEn ) begin
		if( C1< 11'd1301 )begin Clkt <= 11'd0; C1 <= C1 + 1'b1; end
		else begin Clkt <= 1'b1; C1 <= 11'd0; end
	end
	else begin Clkt <= 1'b0; C1 <= 11'd0; end


reg IsSta1,IsSta2;
always @ (posedge	Clk) begin //外部输入信号2次寄存,消除亚稳态
	IsSta1<=IsSta;IsSta2<=IsSta1;
end

parameter IDLE = 1'b0;
parameter SEND = 1'b1;

reg [0:0]s;
reg Txd;
reg IsDone;
reg [7:0] DBin [3:0] ;
reg [9:0] Dsin;
reg [2:0] C2;
wire TxdUp; 
reg [3:0]i;

assign TxdUp = IsSta1 & (!IsSta2); 

always @(posedge Clk ) begin 
	if( TxdUp )begin //fifo
		DBin[0] <= Din; 
		DBin[1] <= DBin[0];
		DBin[2] <= DBin[1];
		DBin[3] <= DBin[2];
		C2 <= C2 + 1'b1;
	end 
	
	if(C2 < 3'd2) IsDone <= 1'b1; else IsDone <= 1'b0;	
		
	case(s)
		IDLE:  
		begin   
		i <= 1'b0;Txd <= 1'b1;ClkEn <= 1'b0; Dsin[0] <= 1'b0; Dsin[9] <= 1'b1; 
		if(C2 > 0&&(!TxdUp) )begin Dsin[8:1] <= DBin[C2-1'b1];C2 <= C2 - 1'b1;s <= SEND;ClkEn <= 1'b1; end  
		end
		SEND:  
		if( Clkt )begin  
			if( i< 4'd10 )begin Txd <= Dsin[i];i <= i + 1'b1;end else s <= IDLE;		 
		end
	endcase
end
endmodule