www.pudn.com > UartLoop.rar > UartRxd.v, change:2013-07-18,size:1498b


/****************************************************************************** 
designer :openpuu.com 
data	   :2013.5.10 
version  :1.1 
name     :uart reciever
******************************************************************************/

`timescale 1 ns / 1 ns
module UartRxd(Clk,Dout,IsDone,Rxd);

input  Clk;
output [7:0] Dout;
output IsDone;
input  Rxd;

reg Clk16; 
reg [6 : 0]C1; 

always @ (posedge	Clk )  
		if( C1 < 7'd80 )begin Clk16 <= 1'b0;C1 <= C1 + 1'b1;end
		else begin Clk16 <= 1'b1; C1 <= 7'd0; end 
		
reg RxdD1,RxdD2;
always @ ( posedge	Clk ) begin 
	RxdD1 <= Rxd; RxdD2 <= RxdD1;
end
 
parameter IDLE= 1'b0;
parameter SAMP= 1'b1; 

reg IsDone;
reg [7:0] Dout;
reg [3:0] C2;
reg [3:0] C3; 
reg [3:0] i; 
reg IsSta= 1'b0; 
reg [0:0]s= 1'b0;
always @(posedge Clk) begin  
	IsDone <= 1'b0;
	case ( s ) 
		IDLE: 
		begin 
			i <= 4'd0; C2 <= 4'd0; C3 <= 4'd0; IsSta<= 1'b0;  
			if( !RxdD2 )begin  s <= SAMP; end 
		end 
		SAMP: 
		if(Clk16)begin 
			if(C2 < 4'd15) begin  
				C2 <= C2 + 1'b1;	 
				if(!RxdD2) C3 <= C3+1; else C3 <= C3; 
				if( i==4'd8&&C2==4'd12 )begin  
						s <= IDLE; if( C3 <4'd6 )IsDone <= 1'b1;											 
				end 
			end
			else begin  
				C2 <= 4'd0; C3 <= 4'd0; 
				if( !IsSta )begin 
				   i <= 4'd0; if( C3 > 4'd7) IsSta <= 1'b1; else begin IsSta <= 1'b0; s<= IDLE; end 
				end 
				else if( i< 4'd8 )begin  
						if( C3 > 4'd7 ) Dout[i] <= 1'b0; else Dout[i] <= 1'b1; i <= i + 1'b1; 
				end		
			end 
		end 
		 
	endcase 
end
endmodule