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LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_ARITH.ALL; 
 
ENTITY fro_light IS 
  PORT(  
       clk       : IN STD_LOGIC; 
       glistenab : IN STD_LOGIC; 
       glisten   : OUT STD_LOGIC 
      ); 
end fro_light; 
 
ARCHITECTURE arch_fro_light OF fro_light IS 
BEGIN 
  process( clk, glistenab) 
  BEGIN   
   if( glistenab = '1')THEN 
       glisten <= clk; 
     else 
       glisten <= '0'; 
     end if; 
  end process; 
end arch_fro_light;