www.pudn.com > 8051-core.rar > Multiply.v, change:2001-08-04,size:2342b


////////////////////////////////////////////////////////////////////// 
//// 								  //// 
//// multiply for 8051 Core 				  	  //// 
//// 								  //// 
//// This file is part of the 8051 cores project 		  //// 
//// http://www.opencores.org/cores/8051/ 			  //// 
//// 								  //// 
//// Description 						  //// 
//// Implementation of multipication used in alu.v 		  //// 
//// 								  //// 
//// To Do: 							  //// 
////  Nothing							  //// 
//// 								  //// 
//// Author(s): 						  //// 
//// - Simon Teran, simont@opencores.org 			  //// 
//// 								  //// 
////////////////////////////////////////////////////////////////////// 
//// 								  //// 
//// Copyright (C) 2001 Authors and OPENCORES.ORG 		  //// 
//// 								  //// 
//// This source file may be used and distributed without 	  //// 
//// restriction provided that this copyright statement is not 	  //// 
//// removed from the file and that any derivative work contains  //// 
//// the original copyright notice and the associated disclaimer. //// 
//// 								  //// 
//// This source file is free software; you can redistribute it   //// 
//// and/or modify it under the terms of the GNU Lesser General   //// 
//// Public License as published by the Free Software Foundation; //// 
//// either version 2.1 of the License, or (at your option) any   //// 
//// later version. 						  //// 
//// 								  //// 
//// This source is distributed in the hope that it will be 	  //// 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   //// 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 	  //// 
//// PURPOSE. See the GNU Lesser General Public License for more  //// 
//// details. 							  //// 
//// 								  //// 
//// You should have received a copy of the GNU Lesser General 	  //// 
//// Public License along with this source; if not, download it   //// 
//// from http://www.opencores.org/lgpl.shtml 			  //// 
//// 								  //// 
////////////////////////////////////////////////////////////////////// 
// 
// ver: 1 
// 
 
 
module multiply (src1, src2, des1, des2, desOv); 
input [7:0] src1, src2; 
output des1, des2, desOv; 
reg desOv; reg [7:0] des1, des2; 
 
always @(src1 or src2) 
begin 
  {des2, des1} = src1* src2; 
  if (des2!=8'b00000000) 
    desOv = 1'b1; 
  else 
    desOv = 1'b0; 
end 
 
endmodule