[file head]:
/******************************************************************************\
* Copyright (C) 2002-2004 Texas Instruments Incorporated.
* All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... csl_vphal.h
* DATE CREATED.. 12/06/2001
* updated for version 1.3.............01/10/2002
* LAST MODIFIED. 08/12/2004 Fixed defintion error in _VP_VDIMGOFFxx_ADDR
* 02/28/2002
*
*------------------------------------------------------------------------------
* REGISTERS
********************************************************************************
* Memory Mapping Register -- Global
*
* VPPID0 - Video Port 0 Peripheral Identification Register
* VPPID1 - Video Port 1 Peripheral Identification Register
* VPPID2 - Video Port 2 Peripheral Identification Register
* PCR0 - Video Port 0 Peripheral Control
* P
... ...

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ADDR (_VP_BFBASE_PORT2 + 4*_VP_YSRCB_OFFSET)

#define _VP_CBSRCB0_ADDR (_VP_BFBASE_PORT0 + 4*_VP_CBSRCB_OFFSET)
#define _VP_CBSRCB1_ADDR (_VP_BFBASE_PORT1 + 4*_VP_CBSRCB_OFFSET)
#define _VP_CBSRCB2_ADDR (_VP_BFBASE_PORT2 + 4*_VP_CBSRCB_OFFSET)

#define _VP_CRSRCB0_ADDR (_VP_BFBASE_PORT0 + 4*_VP_CRSRCB_OFFSET)
#define _VP_CRSRCB1_ADDR (_VP_BFBASE_PORT1 + 4*_VP_CRSRCB_OFFSET)
#define _VP_CRSRCB2_ADDR (_VP_BFBASE_PORT2 + 4*_VP_CRSRCB_OFFSET)

#define _VP_YDSTB0_ADDR (_VP_BFBASE_PORT0 + 4*_VP_YDSTB_OFFSET)
#define _VP_YDSTB1_ADDR (_VP_BFBASE_PORT1 + 4*_VP_YDSTB_OFFSET)
#define _VP_YDSTB2_ADDR (_VP_BFBASE_PORT2 + 4*_VP_YDSTB_OFFSET)
#endif


/*----------------------------------------------------------------------------*/

#endif /* VP_SUPPORT */
#endif /* _CSL_VPHAL_H_ */
/******************************************************************************\
* End of csl_vphal.h
\******************************************************************************/