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--ACS_2.vhd  
--add-compare-select unit of viterbi 
--v0.1 
 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
 
entity ACS_2 is 
	port( 
		clk: in std_logic; 
		reset: in std_logic; 
		rc : in std_logic_vector(1 downto 0); 
		im_1: in std_logic_vector(5 downto 0); 
		im_3: in std_logic_vector(5 downto 0); 
		acs_2: out std_logic; 
		om_2: out std_logic_vector(5 downto 0) 
		); 
end ACS_2; 
 
architecture a of ACS_2 is 
 
begin 
	process(clk,reset) 
	variable mc_1: std_logic_vector(1 downto 0); 
	variable mc_3: std_logic_vector(1 downto 0); 
	variable up  : unsigned(5 downto 0); 
	variable low : unsigned(5 downto 0); 
	begin	 
		if rising_edge(clk) then 
			if reset='1' then 
				mc_1:="00"; 
				mc_3:="00"; 
				acs_2<='0'; 
				om_2<="100000"; 
			else 
			mc_1(0):=(not rc(0)) xor rc(1);   
			mc_1(1):=(not rc(0)) and rc(1);   
			mc_3(0):= rc(0) xor (not rc(1)); 
			mc_3(1):= rc(0) and (not rc(1)); 
			 
			up:=unsigned(im_1)+unsigned(mc_1); 
			low:=unsigned(im_3)+unsigned(mc_3); 
			 
				if up<=low then 
					acs_2<='0'; 
					om_2<=conv_std_logic_vector(up,6); 
				else 
					acs_2<='1'; 
					om_2<=conv_std_logic_vector(low,6); 
				end if;		 
			end if; 
		end if; 
	end process; 
end a;