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# Copyright (C) 1991-2006 Altera Corporation 
# Your use of Altera Corporation's design tools, logic functions  
# and other software and tools, and its AMPP partner logic  
# functions, and any output files any of the foregoing  
# (including device programming or simulation files), and any  
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License  
# Subscription Agreement, Altera MegaCore Function License  
# Agreement, or other applicable license agreement, including,  
# without limitation, that your use is for the sole purpose of  
# programming logic devices manufactured by Altera and sold by  
# Altera or its authorized distributors.  Please refer to the  
# applicable agreement for further details. 
 
 
# The default values for assignments are stored in the file 
#		ACS_0_assignment_defaults.qdf 
# If this file doesn't exist, and for assignments not listed, see file 
#		assignment_defaults.qdf 
 
# Altera recommends that you do not modify this file. This 
# file is updated automatically by the Quartus II software 
# and any changes you make may be lost or overwritten. 
 
 
set_global_assignment -name FAMILY Stratix 
set_global_assignment -name DEVICE AUTO 
set_global_assignment -name TOP_LEVEL_ENTITY ACS_0 
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:15:07  OCTOBER 02, 2006" 
set_global_assignment -name LAST_QUARTUS_VERSION 6.0 
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST 
set_global_assignment -name VHDL_FILE ACS_0.vhd 
set_global_assignment -name VECTOR_WAVEFORM_FILE ACS_0.vwf 
set_global_assignment -name VHDL_FILE ACS_1.vhd 
set_global_assignment -name VHDL_FILE ACS_2.vhd 
set_global_assignment -name VHDL_FILE ACS_3.vhd