www.pudn.com > scaling.rar > evmdm642_edma_aic23.h
/* * Copyright 2003 by Texas Instruments Incorporated. * All rights reserved. Property of Texas Instruments Incorporated. * Restricted rights to use, duplicate or disclose this code are * granted through contract. * */ /* "@(#) DDK 1.10.00.23 07-02-03 (ddk-b12)" */ /* * ======== evmdm642_edma_aic23.h ======== */ #ifndef EVMDM642_EDMA_AIC23_ #define EVMDM642_EDMA_AIC23_ #include#include #include #ifdef __cplusplus extern "C" { #endif #define IOM_CNTL_AUDIO_SETSAMPLERATE IOM_USER + 4 /* Version number definition */ #define EVMDM642_EDMA_AIC23_VERSION_1 0xAB01 /* Default IRQ number for EDMA is 8 */ #define EVMDM642_EDMA_AIC23_EDMA_ID_DEFAULT 8 #define EVMDM642_EDMA_AIC23_INTR_MASK_DEFAULT 0xffff /* DM642 prototype EVM codec clock frequency 12.288Mhz */ #define AIC23_REG8_12288 \ AIC23_9BITWORD( /* REG 8: sample rate control */ \ 0, /* reserved */ \ 0, /* clock output divider: 1 (MCLK) */ \ 0, /* clock input divider: 1 (MCLK) */ \ 0,0,0,0,0, /* sampling rate: ADC 48kHz DAC 48kHz */ \ 0 /* clock mode select (USB/normal): normal */ \ ) /* DM642 production EVM codec clock frequency 18.432Mhz */ #define AIC23_REG8_18432 \ AIC23_9BITWORD( /* REG 8: sample rate control */ \ 0, /* reserved */ \ 0, /* clock output divider: 1 (MCLK) */ \ 0, /* clock input divider: 1 (MCLK) */ \ 0,0,0,0,1, /* sampling rate: ADC 48kHz DAC 48kHz */ \ 0 /* clock mode select (USB/normal): normal */ \ ) /* * define an AIC23_DEFAULTPARAMS with 10 default register values * for DM642 production EVM */ #define AIC23_DEFAULTPARAMS_EVMDM642 { \ AIC23_REG0_DEFAULT, \ AIC23_REG1_DEFAULT, \ AIC23_REG2_DEFAULT, \ AIC23_REG3_DEFAULT, \ AIC23_REG4_DEFAULT, \ AIC23_REG5_DEFAULT, \ AIC23_REG6_DEFAULT, \ AIC23_REG7_DEFAULT, \ AIC23_REG8_18432, \ AIC23_REG9_DEFAULT \ } #define EVMDM642_EDMA_AIC23_DEFAULT_DEVPARAMS { \ EVMDM642_EDMA_AIC23_VERSION_1, \ TRUE, /* Buffers are in external memory by default */ \ /* Driver disable the McASP high frequecy rate generator */ \ C6X1X_EDMA_MCASP_EXTERNAL, \ /* Driver disable the McASP clk rate generator */ \ C6X1X_EDMA_MCASP_EXTERNAL, \ /* Driver disable the McASP frame sync generator */ \ C6X1X_EDMA_MCASP_EXTERNAL, \ EVMDM642_EDMA_AIC23_EDMA_ID_DEFAULT, /* Default IRQ number is 8 */ \ -1, /* use default */ \ -1, /* use default */ \ NULL, /* do not register mcasp event */ \ EVMDM642_EDMA_AIC23_INTR_MASK_DEFAULT, \ EVMDM642_EDMA_AIC23_INTR_MASK_DEFAULT, \ EVMDM642_EDMA_AIC23_INTR_MASK_DEFAULT, \ AIC23_DEFAULTPARAMS_EVMDM642 \ } /* Driver function table to be used by applications. */ extern far IOM_Fxns EVMDM642_EDMA_AIC23_FXNS; /* Device setup parameters */ typedef struct EVMDM642_EDMA_AIC23_DevParams { Int versionId; /* Set to the version number used by the application */ Bool cacheCalls; /* Set to TRUE if buffers are in external memory */ Uns enableClkg; /* Set VALUE for internal clock generator */ Uns enableHclkg; /* Set VALUE for internal high frequency clock generator */ Uns enableFsyncg; /* Set VALUE for internal framesync generator */ Int irqId; /* IRQ number to use for EDMA interrupt */ Int inEvtIrqId; /* IRQ number used for McASP Event interrupt */ Int outEvtIrqId; /* IRQ number used for McASP Event interrupt */ C6X1X_EDMA_MCASP_EvtCallback *evtCallback; /* Register events callback */ Uns inEvtIntrMask; /* Interrupt mask, set while executing input ISR */ Uns outEvtIntrMask; /* Interrupt mask, set while executing output ISR */ Uns edmaIntrMask; AIC23_Params aic23Config; } EVMDM642_EDMA_AIC23_DevParams; #ifdef __cplusplus } #endif /* extern "C" */ #endif /* EVMDM642_EDMA_AIC23_ */