www.pudn.com > ccs_encoder.rar > cbp.asm
;******************************************************************************
;* TMS320C6x C/C++ Codegen PC Version 4.32 *
;* Date/Time created: Fri Apr 22 10:36:58 2005 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C621x *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed *
;* Based on options: -o3, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Large *
;* Calls to RTS : Far *
;* Pipelining : Enabled *
;* Speculative Load : Enabled *
;* Memory Aliases : Presume are aliases (pessimistic) *
;* Debug Info : COFF Debug *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.file "cbp.c"
.global _calc_cbp
_calc_cbp: .usect ".far",4,4
.sym _calc_cbp,_calc_cbp, 158, 2, 32
; E:\ti\c6000\cgtools\bin\opt6x.exe -v6210 -O3 C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\TI50520_2 C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\TI50520_5 -w E:/ccs_dct_q/ccs_encoder01-15/ccs_encoder/Debug
.sect ".text"
.global _calc_cbp_plain
.sym _calc_cbp_plain,_calc_cbp_plain, 46, 2, 0
.func 39
;******************************************************************************
;* FUNCTION NAME: _calc_cbp_plain *
;* *
;* Regs Modified : A0,A3,A4,A5,A6,A7,B0,B1,B2,B4,B5,B6,B7,B8 *
;* Regs Used : A0,A3,A4,A5,A6,A7,B0,B1,B2,B3,B4,B5,B6,B7,B8,DP,SP *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
;******************************************************************************
;* *
;* Using -g (debug) with optimization (-o3) may disable key optimizations! *
;* *
;******************************************************************************
_calc_cbp_plain:
;** --------------------------------------------------------------------------*
.line 2
.sym _codes,4, 19, 17, 32
.sym _codes,23, 19, 4, 32
.sym _i,6, 4, 4, 32
.sym _cbp,7, 14, 4, 32
MV .S2X A4,B7 ; |40|
.line 6
MVK .S2 0x6,B2 ; |44|
MVK .S2 0x2,B5
.line 4
ZERO .D1 A7 ; |42|
.line 6
ZERO .D1 A6 ; |44|
;** --------------------------------------------------------------------------*
;** BEGIN LOOP L1
;** --------------------------------------------------------------------------*
L1:
ADD .D2 B5,B7,B4
SUB .S1X B4,2,A0
.line 7
MVC .S2 CSR,B6
LDH .D1T1 *++A0,A3 ; |46| (P) <0,0>
|| AND .S2 -2,B6,B8
MVC .S2 B8,CSR ; interrupts off
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 45
;* Loop opening brace source line : 45
;* Loop closing brace source line : 50
;* Known Minimum Trip Count : 1
;* Known Maximum Trip Count : 63
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 2
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 1 0
;* .S units 0 1
;* .D units 1 0
;* .M units 0 0
;* .X cross paths 0 1
;* .T address paths 1 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 1 1 (.L or .S unit)
;* Addition ops (.LSD) 2 2 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 2*
;*
;* Searching for software pipeline schedule at ...
;* ii = 2 Schedule found with 8 iterations in parallel
;*
;* Register Usage Table:
;* +---------------------------------+
;* |AAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBB|
;* |0000000000111111|0000000000111111|
;* |0123456789012345|0123456789012345|
;* |----------------+----------------|
;* 0: |* *** |* * |
;* 1: |* *** |** * |
;* +---------------------------------+
;*
;* Done
;*
;* Collapsed epilog stages : 7
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 14 bytes
;* Minimum threshold value : -mh28
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A5
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C18:
;* 0 LDH .D1T1 *++A0,A4 ; |46|
;* 1 NOP 4
;* 5 CMPEQ .L1 A4,0,A4 ; |46|
;* 6 XOR .S1 1,A4,A3 ; |46|
;* 7 SUB .D1 A3,1,A3 ; |46|
;* || SUB .D2 B4,1,B4 ; |50| Define a twin register
;* 8 AND .L2X A3,B4,B1 ; |50|
;* || [ B0] MV .L1 A3,A5 ; |50|
;* 9 [!B1] ZERO .S2 B0
;* 10 [ B0] B .S2 C18 ; |50|
;* 11 NOP 5
;* ; BRANCH OCCURS ; |50|
;*
;* RESTORE CODE
;*
;* MV A5,A3
;*----------------------------------------------------------------------------*
L2: ; PIPED LOOP PROLOG
LDH .D1T1 *++A0,A3 ; |46| (P) <1,0>
NOP 1
LDH .D1T1 *++A0,A4 ; |46| (P) <2,0>
CMPEQ .L1 A3,0,A3 ; |46| (P) <0,5>
MVK .S2 0x3f,B4 ; |45|
|| XOR .S1 1,A3,A4 ; |46| (P) <0,6>
|| LDH .D1T1 *++A0,A3 ; |46| (P) <3,0>
ZERO .D1 A5
|| MVK .S2 0x1,B0
|| SUB .D2 B4,1,B4 ; |50| (P) <0,7> Define a twin register
|| SUB .S1 A4,1,A3 ; |46| (P) <0,7>
|| CMPEQ .L1 A3,0,A4 ; |46| (P) <1,5>
[ B0] MV .L1 A3,A5 ; |50| (P) <0,8>
|| AND .S2X A3,B4,B1 ; |50| (P) <0,8>
|| XOR .S1 1,A4,A3 ; |46| (P) <1,6>
|| LDH .D1T1 *++A0,A3 ; |46| (P) <4,0>
[!B1] ZERO .D2 B0 ; (P) <0,9>
|| SUB .S2 B4,1,B4 ; |50| (P) <1,7> Define a twin register
|| SUB .D1 A3,1,A3 ; |46| (P) <1,7>
|| CMPEQ .L1 A4,0,A4 ; |46| (P) <2,5>
[ B0] MV .L1 A3,A5 ; |50| (P) <1,8>
|| AND .L2X A3,B4,B1 ; |50| (P) <1,8>
|| XOR .S1 1,A4,A4 ; |46| (P) <2,6>
|| LDH .D1T1 *++A0,A4 ; |46| (P) <5,0>
|| [ B0] B .S2 L3 ; |50| (P) <0,10>
[!B1] ZERO .D2 B0 ; (P) <1,9>
|| SUB .S2 B4,1,B4 ; |50| (P) <2,7> Define a twin register
|| SUB .D1 A4,1,A3 ; |46| (P) <2,7>
|| CMPEQ .L1 A3,0,A4 ; |46| (P) <3,5>
[ B0] B .S2 L3 ; |50| (P) <1,10>
|| [ B0] MV .L1 A3,A5 ; |50| (P) <2,8>
|| AND .L2X A3,B4,B1 ; |50| (P) <2,8>
|| XOR .S1 1,A4,A4 ; |46| (P) <3,6>
|| LDH .D1T1 *++A0,A4 ; |46| (P) <6,0>
[!B1] ZERO .D2 B0 ; (P) <2,9>
|| SUB .S2 B4,1,B4 ; |50| (P) <3,7> Define a twin register
|| SUB .D1 A4,1,A3 ; |46| (P) <3,7>
|| CMPEQ .L1 A3,0,A4 ; |46| (P) <4,5>
;** --------------------------------------------------------------------------*
L3: ; PIPED LOOP KERNEL
[ B0] B .S2 L3 ; |50| <2,10>
|| [ B0] MV .L1 A3,A5 ; |50| <3,8>
|| AND .L2X A3,B4,B1 ; |50| <3,8>
|| XOR .S1 1,A4,A3 ; |46| <4,6>
|| LDH .D1T1 *++A0,A4 ; |46| <7,0>
[!B1] ZERO .S2 B0 ; <3,9>
|| SUB .D2 B4,1,B4 ; |50| <4,7> Define a twin register
|| SUB .D1 A3,1,A3 ; |46| <4,7>
|| CMPEQ .L1 A4,0,A4 ; |46| <5,5>
;** --------------------------------------------------------------------------*
L4: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
SUB .S1 5,A6,A3
|| CMPEQ .L1 A5,0,A0
SHL .S1 A0,A3,A0
OR .S1 A0,A7,A7
|| MVC .S2 B6,CSR ; interrupts on
.line 10
ADDK .S2 128,B5 ; |48|
.line 13
ADD .D1 1,A6,A6 ; |51|
|| SUB .D2 B2,1,B2 ; |51|
[ B2] B .S2 L1 ; |51|
NOP 5
; BRANCH OCCURS ; |51|
;** --------------------------------------------------------------------------*
.line 14
MV .D1 A7,A4 ; |52|
.line 15
RET .S2 B3 ; |53|
NOP 5
; BRANCH OCCURS ; |53|
.endfunc 53,000000000h,0
.sect ".text"
.global _calc_cbp_c
.sym _calc_cbp_c,_calc_cbp_c, 46, 2, 0
.func 57
;******************************************************************************
;* FUNCTION NAME: _calc_cbp_c *
;* *
;* Regs Modified : A0,A1,A3,A4,A5,A6,B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10, *
;* SP *
;* Regs Used : A0,A1,A3,A4,A5,A6,B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10, *
;* SP *
;* Local Frame Size : 0 Args + 0 Auto + 8 Save = 8 byte *
;******************************************************************************
;******************************************************************************
;* *
;* Using -g (debug) with optimization (-o3) may disable key optimizations! *
;* *
;******************************************************************************
_calc_cbp_c:
;** --------------------------------------------------------------------------*
.line 2
.sym _codes,4, 19, 17, 32
.sym _cbp,4, 14, 4, 32
.sym _i,17, 14, 4, 32
.sym _codes,20, 19, 4, 32
.sym _codes,0, 19, 4, 32
STW .D2T2 B10,*SP--(8) ; |58|
STW .D2T2 B3,*+SP(4) ; |58|
ADD .S2X 2,A4,B4
.line 3
MVK .S2 0x6,B1 ; |59|
.line 4
ZERO .D1 A4 ; |60|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;* Disqualified loop: Loop contains control code
;*----------------------------------------------------------------------------*
L5:
.line 14
ADD .D1 A4,A4,A4 ; |70|
.line 15
LDH .D2T2 *B4,B0 ; |71|
NOP 4
[ B0] B .S1 L6 ; |71|
[!B0] ADD .D2 2,B4,B5 ; |71|
[!B0] LDW .D2T2 *B5,B0 ; |71|
NOP 3
; BRANCH OCCURS ; |71|
;** --------------------------------------------------------------------------*
NOP 1
[ B0] B .S1 L6 ; |71|
NOP 5
; BRANCH OCCURS ; |71|
;** --------------------------------------------------------------------------*
.line 18
ADD .D2 B4,22,B6 ; |74|
|| ADD .S2 6,B4,B5 ; |74|
LDW .D2T2 *B5,B7 ; |74|
|| ADD .S1X 14,B4,A0 ; |74|
LDW .D2T2 *+B5(4),B8 ; |74|
|| LDW .D1T1 *A0,A3 ; |74|
LDW .D1T1 *+A0(4),A0 ; |74|
|| LDW .D2T2 *B6,B5 ; |74|
LDW .D2T2 *+B6(4),B6 ; |74|
NOP 2
OR .S2X A3,B7,B7 ; |74|
OR .S1X A0,B8,A0 ; |74|
|| OR .S2 B5,B7,B5 ; |74|
OR .S2X B6,A0,B5 ; |74|
|| CMPEQ .L2 0,B5,B0 ; |74|
[ B0] CMPEQ .L2 0,B5,B0 ; |74|
[!B0] B .S1 L6 ; |74|
NOP 5
; BRANCH OCCURS ; |74|
;** --------------------------------------------------------------------------*
.line 21
ADD .D2 B4,30,B5 ; |77|
ADDAH .D2 B4,19,B8 ; |77|
ADDAH .D2 B4,23,B7 ; |77|
ADDAH .D2 B4,27,B6 ; |77|
LDW .D2T2 *B5,B9 ; |77|
LDW .D2T2 *B8,B10 ; |77|
LDW .D2T2 *B7,B0 ; |77|
LDW .D2T2 *+B7(4),B3 ; |77|
LDW .D2T2 *+B5(4),B5 ; |77|
LDW .D2T2 *+B8(4),B8 ; |77|
LDW .D2T2 *B6,B7 ; |77|
LDW .D2T2 *+B6(4),B2 ; |77|
OR .S2 B10,B9,B6 ; |77|
NOP 1
OR .S2 B0,B6,B5 ; |77|
|| OR .L2 B8,B5,B6 ; |77|
OR .S2 B7,B5,B6 ; |77|
|| OR .L2 B3,B6,B5 ; |77|
OR .S2 B2,B5,B5 ; |77|
|| CMPEQ .L2 0,B6,B0 ; |77|
[ B0] CMPEQ .L2 0,B5,B0 ; |77|
[!B0] B .S1 L6 ; |77|
NOP 5
; BRANCH OCCURS ; |77|
;** --------------------------------------------------------------------------*
.line 24
ADDAH .D2 B4,31,B5 ; |80|
LDW .D2T2 *+B5(4),B0 ; |80|
|| MVK .S2 70,B6 ; |80|
ADD .S2 B6,B4,B5 ; |80|
|| LDW .D2T2 *B5,B9 ; |80|
LDW .D2T2 *+B5(4),B8 ; |80|
|| MVK .S1 78,A0 ; |80|
MVK .S2 86,B5 ; |80|
|| LDW .D2T2 *B5,B7 ; |80|
|| ADD .S1X A0,B4,A0 ; |80|
ADD .D2 B5,B4,B5 ; |80|
|| LDW .D1T1 *A0,A3 ; |80|
LDW .D2T2 *B5,B6 ; |80|
LDW .D1T1 *+A0(4),A0 ; |80|
LDW .D2T2 *+B5(4),B5 ; |80|
OR .S2 B7,B9,B7 ; |80|
OR .S1X A3,B7,A3 ; |80|
OR .S1X B6,A3,A3 ; |80|
|| OR .S2 B8,B0,B7 ; |80|
OR .S1X A0,B7,A0 ; |80|
OR .S1X B5,A0,A0 ; |80|
|| CMPEQ .L1 0,A3,A1 ; |80|
[ A1] CMPEQ .L1 0,A0,A1 ; |80|
[!A1] B .S1 L6 ; |80|
NOP 5
; BRANCH OCCURS ; |80|
;** --------------------------------------------------------------------------*
.line 27
MVK .S2 94,B5 ; |83|
ADD .D2 B5,B4,B5 ; |83|
|| MVK .S2 110,B7 ; |83|
|| MVK .S1 102,A0 ; |83|
LDW .D2T2 *B5,B6 ; |83|
|| ADD .S1X A0,B4,A0 ; |83|
|| ADD .S2 B7,B4,B7 ; |83|
LDW .D2T2 *B7,B8 ; |83|
|| LDW .D1T1 *A0,A3 ; |83|
|| MVK .S1 118,A5 ; |83|
LDW .D2T2 *+B5(4),B5 ; |83|
|| LDW .D1T1 *+A0(4),A0 ; |83|
|| ADD .S1X A5,B4,A5 ; |83|
LDW .D2T2 *+B7(4),B7 ; |83|
|| LDW .D1T1 *A5,A6 ; |83|
LDW .D1T1 *+A5(4),A5 ; |83|
NOP 1
OR .S2X A3,B6,B6 ; |83|
OR .L2X A0,B5,B5 ; |83|
|| OR .S2 B8,B6,B6 ; |83|
OR .S2 B7,B5,B5 ; |83|
|| OR .S1X A6,B6,A0 ; |83|
OR .S1X A5,B5,A0 ; |83|
|| CMPEQ .L1 0,A0,A1 ; |83|
[ A1] CMPEQ .L1 0,A0,A1 ; |83|
XOR .S1 1,A1,A0 ; |83|
ADD .D1 A0,A4,A4 ; |83|
.line 28
B .S1 L7 ; |84|
NOP 5
; BRANCH OCCURS ; |84|
;** --------------------------------------------------------------------------*
L6:
.line 16
ADD .D1 1,A4,A4 ; |72|
;** --------------------------------------------------------------------------*
L7:
.line 30
ADDK .S2 128,B4 ; |86|
.line 31
SUB .D2 B1,1,B1 ; |87|
[ B1] B .S1 L5 ; |87|
NOP 5
; BRANCH OCCURS ; |87|
;** --------------------------------------------------------------------------*
.line 34
.line 35
LDW .D2T2 *+SP(4),B3 ; |91|
LDW .D2T2 *++SP(8),B10 ; |91|
NOP 3
RET .S2 B3 ; |91|
NOP 5
; BRANCH OCCURS ; |91|
.endfunc 91,004080000h,8
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
.sym _cbpFunc, 0, 46, 13, 0
.sym _cbpFuncPtr, 0, 158, 13, 32