www.pudn.com > vxworks0108.rar > vmLib.h
/* vmLib.h - header for architecture independent mmu interface */
#ifndef __INCvmLibh
#define __INCvmLibh
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "mmu603lib.h"
/* status codes */
#define S_vmLib_NOT_PAGE_ALIGNED (M_vmLib | 1)
#define S_vmLib_BAD_STATE_PARAM (M_vmLib | 2)
#define S_vmLib_BAD_MASK_PARAM (M_vmLib | 3)
#define S_vmLib_ADDR_IN_GLOBAL_SPACE (M_vmLib | 4)
#define S_vmLib_TEXT_PROTECTION_UNAVAILABLE (M_vmLib | 5)
#if (CPU_FAMILY == ARM)
#define S_vmLib_NO_FREE_REGIONS (M_vmLib | 6)
#define S_vmLib_ADDRS_NOT_EQUAL (M_vmLib | 7)
#endif
/* physical memory descriptor is used to map virtual memory in sysLib
* and usrConfig.
*/
typedef struct phys_mem_desc
{
void *virtualAddr;
void *physicalAddr;
UINT len;
UINT initialStateMask; /* mask parameter to vmStateSet */
UINT initialState; /* state parameter to vmStateSet */
} PHYS_MEM_DESC;
IMPORT PHYS_MEM_DESC sysPhysMemDesc[];
IMPORT int sysPhysMemDescNumEnt;
/* state mask constants for vmStateSet vmStateGet. These
* constants define the bit fields in the page state.
*/
#define VM_STATE_MASK_VALID 0x03
#define VM_STATE_MASK_WRITABLE 0x0c
#define VM_STATE_MASK_CACHEABLE 0x30
#define VM_STATE_MASK_MEM_COHERENCY 0x40
#define VM_STATE_MASK_GUARDED 0x80
/* state mask constant for ARM: bufferable, not cacheable */
#define VM_STATE_MASK_BUFFERABLE 0x80
/* additional state mask constants for XScale: extended page table support */
#define VM_STATE_MASK_EX_CACHEABLE 0x40
#define VM_STATE_MASK_EX_BUFFERABLE 0xC0
/* state constants for vmStateSet and vmStateGet. These
* values are or'ed together to form the page state. Additional
* values may be defined by specific architectures below.
*/
#define VM_STATE_VALID 0x01
#define VM_STATE_VALID_NOT 0x00
#define VM_STATE_WRITABLE 0x04
#define VM_STATE_WRITABLE_NOT 0x00
#define VM_STATE_CACHEABLE 0x10
#define VM_STATE_CACHEABLE_NOT 0x00
/* additional cache states for MC68040 and ARM710A */
#define VM_STATE_CACHEABLE_WRITETHROUGH 0x20
/* additional cache states for MC68040 */
#define VM_STATE_CACHEABLE_NOT_NON_SERIAL 0x30
/* additional cache states for MC68060 */
#define VM_STATE_CACHEABLE_NOT_IMPRECISE 0x30
/* additional cache states for the powerPc */
#define VM_STATE_MEM_COHERENCY 0x40
#define VM_STATE_MEM_COHERENCY_NOT 0x00
#define VM_STATE_GUARDED 0x80
#define VM_STATE_GUARDED_NOT 0x00
#define VM_STATE_ACCESS_NOT 0x08
/* since MEM_COHERENCY and GUARDED state bits are already added,
* we use them for Pentium by renaming it as follows:
* VM_STATE_WBACK = VM_STATE_MEM_COHERENCY
* VM_STATE_WBACK_NOT = VM_STATE_MEM_COHERENCY_NOT
* VM_STATE_GLOBAL = VM_STATE_GUARDED
* VM_STATE_GLOBAL_NOT = VM_STATE_GUARDED_NOT
* their meanings are:
* VM_STATE_WBACK = set page cache-write-back bit
* VM_STATE_WBACK_NOT = not set page cache-write-back bit
* VM_STATE_GLOBAL = set page global bit
* VM_STATE_GLOBAL_NOT = not set page global bit
*/
#define VM_STATE_MASK_WBACK VM_STATE_MASK_MEM_COHERENCY
#define VM_STATE_MASK_GLOBAL VM_STATE_MASK_GUARDED
#define VM_STATE_WBACK VM_STATE_MEM_COHERENCY
#define VM_STATE_WBACK_NOT VM_STATE_MEM_COHERENCY_NOT
#define VM_STATE_GLOBAL VM_STATE_GUARDED
#define VM_STATE_GLOBAL_NOT VM_STATE_GUARDED_NOT
/* additional cache state for ARM: bufferable, not cacheable */
#define VM_STATE_BUFFERABLE 0x80
#define VM_STATE_BUFFERABLE_NOT 0x00
/* additional cache states for XScale: extended page table support */
#define VM_STATE_EX_CACHEABLE 0x40
#define VM_STATE_EX_CACHEABLE_NOT 0x00
#define VM_STATE_EX_BUFFERABLE 0xC0
#define VM_STATE_EX_BUFFERABLE_NOT 0x00
/* additional cache states for ARM SA-1100 */
#define VM_STATE_CACHEABLE_MINICACHE 0x30
/* additional device type states for sun1e */
#define VM_STATE_MASK_DEVICE_SPACE 0xc0
#define VM_STATE_DS_MEM 0x00
#define VM_STATE_DS_IO 0x40
#define VM_STATE_DS_VME_D16 0x80
#define VM_STATE_DS_VME_D32 0xc0
#endif /* __INCvmLibh */