www.pudn.com > vxworks0108.rar > vg4.h
/* vg4.h - SBS Technologies VG4 board header */
/*
This file contains I/O addresses and related constants for the
VG4 VME board from SBS Technologies.
*/
#ifndef INC_vg4_h
#define INC_vg4_h
#ifdef __cplusplus
extern "C" {
#endif
#define INCLUDE_PCI /* always include pci */
/* Generic macros */
/* Common I/O synchronizing instructions */
#ifndef EIEIO_SYNC
# define EIEIO_SYNC __asm(" eieio; sync")
#endif /* EIEIO_SYNC */
#ifndef ISYNC
# define ISYNC __asm(" isync")
#endif /* ISYNC */
#ifndef EIEIO
# define EIEIO __asm(" eieio")
#endif /* EIEIO */
/* Translation macro */
#define TRANSLATE(x,y,z)\
((UINT)(x) - (UINT)(y) + (UINT)(z))
/* Legacy ISA space size. Reserved for kybd, com1, com2,... */
#define ISA_LEGACY_SIZE 0x00004000
#define _CACHE_ALIGN_SIZE 32 /* cache line size */
#define BUS VME_BUS
#define PCI_LAT_TIMER 0xff /* default latency timer value */
#define PCI_CLINE_SZ ( _CACHE_ALIGN_SIZE / 4 )
#undef PCI_MAX_BUS
#define PCI_MAX_BUS 0x32 /* MAX # of PCI buses expected */
#define PSWAP(x) LONGSWAP(x) /* swap the long word */
/* Dec 21143 (unit 0) vector and level */
#define INT_VEC_DC LN_INT_VEC /* interrupt vector PCI slot 2 */
#define INT_LVL_DC LN_INT_LVL /* interrupt level PCI slot 2 */
#define DC_POOL_ADRS (NONE) /* NONE = allocate from mem */
#define DC_POOL_SIZE (NONE) /* memory pool size use default */
#define DC_DATA_WIDTH (NONE) /* all data widths */
#define IO_ADRS_DC (char *)(LAN_BASE_ADRS) /* I/O adrs MAP A */
#define DC_RAM_PCI_ADRS (PCI2DRAM_BASE_ADRS) /* RAM seen from PCI MAP A */
#define DC_MODE 0x8 /* default mode */
/* PCI I/O function defines */
#define INT_NUM_IRQ0 INT_VEC_IRQ0
#ifndef _ASMLANGUAGE
#ifndef PCI_IN_BYTE
#define PCI_IN_BYTE(x) sysPciInByte (x)
IMPORT UINT8 sysPciInByte (UINT32 address);
#endif
#ifndef PCI_IN_WORD
#define PCI_IN_WORD(x) sysPciInWord (x)
IMPORT UINT16 sysPciInWord (UINT32 address);
#endif
#ifndef PCI_IN_LONG
#define PCI_IN_LONG(x) sysPciInLong (x)
IMPORT UINT32 sysPciInLong (UINT32 address);
#endif
#ifndef PCI_OUT_BYTE
#define PCI_OUT_BYTE(x,y) sysPciOutByte (x,y)
IMPORT void sysPciOutByte (UINT32 address, UINT8 data);
#endif
#ifndef PCI_OUT_WORD
#define PCI_OUT_WORD(x,y) sysPciOutWord (x,y)
IMPORT void sysPciOutWord (UINT32 address, UINT16 data);
#endif
#ifndef PCI_OUT_LONG
#define PCI_OUT_LONG(x,y) sysPciOutLong (x,y)
IMPORT void sysPciOutLong (UINT32 address, UINT32 data);
#endif
#endif /* _ASMLANGUAGE */
/*
* Shared Memory Interrupt Type.
* Interrupt this target with a 1-byte write mailbox.
* VME_A32 space, address based on procNum, value is ignored.
*/
#define SM_INT_ARG1 VME_AM_EXT_SUP_DATA
#define SM_INT_ARG2 sysVmeMailboxAddrGet(0)
#define SM_INT_ARG3 0xff
/*
* Semaphore Test-and-Set Register as seen from a slave
* Only used with a special version of sysBusTas().
*/
#define OFFBRD_VME_SEM_REG1 (CPU_VME_WINDOW_REG_BASE + \
(CPU_VME_SEM_REG1 - CPU_VME_HW_REGS_BASE))
/*
* PCI Device/Vendor IDs
*/
#define PCI_ID_CHAPARRAL 0x00041057 /* Id for MPC107 */
#define PCI_ID_UNIVERSE 0x000010e3 /* Id for Universe VME chip */
#define PCI_ID_VME PCI_ID_UNIVERSE
#define PCI_ID_NCR875 0x000F1000 /* Id for SYM53c875 */
#define PCI_ID_SCSI PCI_ID_NCR875
#define PCI_ID_LN_DEC21143 0x00191011 /* Id DEC chip 21143 */
#define PCI_ID_LN_DEC PCI_ID_LN_DEC21143
#define PCI_ID_M1543C 0x153310b9 /* Id for ALI M1543C (southbridge) */
#define PCI_ID_IBC PCI_ID_M1543C
#define PCI_ID_M5237 0x523710b9 /* Id for USB M5237 (southbridge) */
#define PCI_ID_USB PCI_ID_M5237
#define PCI_ID_M5229 0x522910b9 /* Id for IDE M5229 (southbridge) */
#define PCI_ID_IDE PCI_ID_M5229
#define PCI_ID_M7101 0x710110b9 /* Id for PMU M7101 (southbridge) */
#define PCI_ID_PMU PCI_ID_M7101
#define PCI_ID_I82559 0x12298086 /* Id for Intel 82559 */
#define PCI_ID_I82559ER 0x12098086 /* Id for Intel 82559 ER */
#define PCI_ID_DEC21152 0x00241011 /* Id for Intel/DEC PCI-to-PCI bridge 21152 */
#define NUM_PCI_DEVS 6 /* No. PCI devices */
#define PCI_DEV_IDSEL_MAX (31-22) /* max # of idsel lines */
#if defined (ADRS_MAP_PREP)
/*
* Memory map as seen from the CPU (PReP)
*/
#define CPU_PCI_ISA_MEM_ADRS 0xc0000000 /* base of PCI/ISA mem space */
#define CPU_PCI_ISA_MEM_SIZE 0x00010000 /* 64 kbytes */
#define CPU_PCI_ISA_IO_ADRS 0x80000000 /* base of PCI/ISA IO space */
#define CPU_PCI_ISA_IO_SIZE 0x00010000 /* 64 kbytes */
#define CPU_PCI_CNFG_ADRS 0x80800000 /* base of PCI config space */
#define CPU_PCI_CNFG_SIZE 0x00800000 /* 8 meg */
#define CPU_PCI_IO_ADRS 0x81000000 /* base of PCI I/O space */
#define CPU_PCI_IO_SIZE 0x3e800000 /* 1G - 24 meg */
#define CPU_PCI_IACK_ADRS 0xbfffe000 /* base of PCI IACK space */
#define CPU_PCI_IACK_SIZE 0x00002000 /* 16 bytes */
#define CPU_PCI_MEM_ADRS 0xc0000000 /* base of PCI memory space */
#define CPU_PCI_MEM_SIZE 0x3f000000 /* 1G - 16 meg */
#define CPU_PCI_MEM_UPPER_ADRS (CPU_PCI_MEM_ADRS>>16)
#else /* defined (ADRS_MAP_PREP) */
/*
* Memory map as seen from the CPU (CHRP)
*/
#define CPU_PCI_ISA_MEM_ADRS 0xfd000000 /* base of PCI/ISA mem space */
/* MPC107 AMBOR[CPU_FD_ALIAS_EN] must be set to 1! */
#define CPU_PCI_ISA_MEM_SIZE 0x00010000 /* 64 kbytes */
#define CPU_PCI_ISA_IO_ADRS 0xfe000000 /* base of PCI/ISA IO space */
#define CPU_PCI_ISA_IO_SIZE 0x00010000 /* 64 kbytes */
#define CPU_PCI_CNFG_ADRS 0xfec00000 /* base of PCI config space */
#define CPU_PCI_CNFG_SIZE 0x00300000 /* 3 meg */
#define CPU_PCI_IO_ADRS 0xfe800000 /* base of PCI I/O space */
#define CPU_PCI_IO_SIZE 0x00400000 /* 4 meg */
#define CPU_PCI_IACK_ADRS 0xfef00000 /* base of PCI IACK space */
#define CPU_PCI_IACK_SIZE 0x00002000 /* 16 bytes */
#define CPU_PCI_MEM_ADRS 0x80000000 /* base of PCI ISA memory space */
#define CPU_PCI_MEM_SIZE 0x01000000 /* 16 meg */
#define CPU_PCI_MEM_UPPER_ADRS (CPU_PCI_MEM_ADRS>>16)
#endif /* defined (ADRS_MAP_PREP) */
/*
* PCI MASTER MEMORY WINDOW LIMITS
*
* These values are strictly defined by the base memory addresses and window
* sizes of the spaces defined above. These values must be correct for the
* sysBusProbe() memory range checks for the PCI bus to work properly.
*/
/* ISA legacy space within PCI MEM space */
#define PCI_MSTR_ISA_MEM_LOCAL CPU_PCI_ISA_MEM_ADRS
#define PCI_MSTR_ISA_MEM_BUS 0x00000000 /* must be zero */
#define PCI_MSTR_ISA_MEM_SIZE CPU_PCI_ISA_MEM_SIZE /* 64 kbytes */
/* ISA legacy space within PCI I/O space */
#define PCI_MSTR_ISA_IO_LOCAL CPU_PCI_ISA_IO_ADRS
#define PCI_MSTR_ISA_IO_BUS 0x00000000 /* must be zero */
#define PCI_MSTR_ISA_IO_SIZE CPU_PCI_ISA_IO_SIZE /* 64 kbytes */
/* PCI I/O space */
#define PCI_MSTR_IO_LOCAL CPU_PCI_IO_ADRS
#if defined (ADRS_MAP_PREP)
# define PCI_MSTR_IO_BUS 0x01000000
#else /* defined (ADRS_MAP_PREP) */
# define PCI_MSTR_IO_BUS 0x00800000
#endif /* defined (ADRS_MAP_PREP) */
#define PCI_MSTR_IO_SIZE 0x00400000 /* 4MB (-> config.h) */
/* PCI (non-prefetchable) memory space */
#define PCI_MSTR_MEMIO_LOCAL CPU_PCI_MEM_ADRS
#if defined (ADRS_MAP_PREP)
# define PCI_MSTR_MEMIO_BUS 0x00000000 /* must be zero */
#else /* defined (ADRS_MAP_PREP) */
# define PCI_MSTR_MEMIO_BUS 0x80000000 /* 1:1 mapping */
#endif /* defined (ADRS_MAP_PREP) */
#define PCI_MSTR_MEMIO_SIZE 0x00800000 /* 8MB (-> config.h) */
/* PCI (pre-fetchable) memory space (above PCI memory space) */
#define PCI_MSTR_MEM_LOCAL (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE)
#define PCI_MSTR_MEM_BUS (PCI_MSTR_MEMIO_BUS + PCI_MSTR_MEMIO_SIZE)
#define PCI_MSTR_MEM_SIZE 0x04000000 /* 64MB (-> config.h) */
/*
* Base address of HW devices as seen from CPU.
*/
/* Embedded Utilities Memory Block */
#define CPU_EUMB_ADRS 0xfdf00000 /* base of EUMB addr */
#define CPU_EUMB_SIZE 0x00100000 /* size of EUMB */
/* Boot flash rom */
#define FLASH_BASE_ADRS 0xFFF00000
#define FLASH_MEM_SIZE 0x00080000
/* Extended flash rom */
#define EXT_FLASH_BASE_ADRS 0x78000000
#define EXT_FLASH_MEM_SIZE 0x04000000 /* max. 64 meg extended flash */
/* NVSRAM */
#define NVSRAM_BASE_ADRS (CPU_PCI_ISA_MEM_ADRS + 0x000F0000)
#define NVSRAM_SIZE 0x00008000
#define NVSRAM_XFL_BOOTADDR 0x7df8
/* Z85230 synchronous & Asynchronous serial communications chip */
#define z85230_PORTA_CTRL (CPU_PCI_ISA_IO_ADRS + 0x0100) /* serial 3 */
#define z85230_PORTA_DATA (CPU_PCI_ISA_IO_ADRS + 0x0101)
#define z85230_PORTB_CTRL (CPU_PCI_ISA_IO_ADRS + 0x0102) /* serial 4 */
#define z85230_PORTB_DATA (CPU_PCI_ISA_IO_ADRS + 0x0103)
/* PCI address space definitions */
#define PCI_ADDR_SPACE_IO 0x00
#define PCI_ADDR_SPACE_MEM 0x01
#define PCI_ADDR_SPACE_ISA_IO 0x02
#define PCI_ADDR_SPACE_ISA_MEM 0x03
/* Memory Map as seen on the PCI bus */
#define PCI_SLV_MEM_LOCAL LOCAL_MEM_LOCAL_ADRS
#if defined (ADRS_MAP_PREP)
# define PCI_SLV_MEM_BUS 0x80000000 /* memory seen from PCI bus */
#else
# define PCI_SLV_MEM_BUS 0x00000000 /* memory seen from PCI bus */
#endif /* defined (ADRS_MAP_PREP) */
#define PCI_SLV_MEM_SIZE DRAM_SIZE
#define PCI2DRAM_BASE_ADRS PCI_SLV_MEM_BUS
#if !defined (INCLUDE_PCI_AUTOCONF)
/*
* Allocate PCI Memory and I/O Space Offsets for PCI devices
*
*/
#define IBC_DEV_SPACE 0x00000
#define LAN_DEV_SPACE 0x20000
#define PMC_DEV_SPACE 0x30000
#define PMC2_DEV_SPACE 0x40000
#define VME_DEV_SPACE 0x50000
#define SCSI_DEV_SPACE 0x60000
/* PCI view of PCI I/O Space for PCI devices */
#define PCI_IO_IBC_ADRS (PCI_MSTR_IO_BUS + IBC_DEV_SPACE) /* IBC I/O */
#define PCI_IO_LN_ADRS (PCI_MSTR_IO_BUS + LAN_DEV_SPACE) /* PCnet */
#define PCI_IO_PMC_ADRS (PCI_MSTR_IO_BUS + PMC_DEV_SPACE) /* extra */
#define PCI_IO_PMC2_ADRS (PCI_MSTR_IO_BUS + PMC2_DEV_SPACE) /* extra */
#define PCI_IO_UNIVERSE_ADRS (PCI_MSTR_IO_BUS + VME_DEV_SPACE) /* UNIVERSE */
/* SCSI */
#if defined (INCLUDE_SCSI_PMC)
# define PCI_IO_SCSI_ADRS (PCI_MSTR_IO_BUS + PMC_DEV_SPACE) /* SCSI on PMC1 */
#elif defined (INCLUDE_SCSI_PMC2)
# define PCI_IO_SCSI_ADRS (PCI_MSTR_IO_BUS + PMC2_DEV_SPACE) /* SCSI on PMC2 */
#else
# define PCI_IO_SCSI_ADRS (PCI_MSTR_IO_BUS + SCSI_DEV_SPACE) /* onboard SCSI */
#endif /* defined (INCLUDE_SCSI_PMC) */
/* PCI view of PCI Memory Space for PCI devices */
#define PCI_MEM_UNIVERSE_ADRS (PCI_MSTR_MEMIO_BUS + VME_DEV_SPACE) /* UNIVERSE */
/* Allocated base address of HW devices as seen from CPU */
#define UNIVERSE_BASE_ADRS (CPU_PCI_MEM_ADRS + VME_DEV_SPACE)
#define LAN_BASE_ADRS (CPU_PCI_IO_ADRS + LAN_DEV_SPACE)
#if defined (INCLUDE_SCSI_PMC)
# define SCSI_BASE_ADRS (CPU_PCI_IO_ADRS + PMC_DEV_SPACE)
#elif defined (INCLUDE_SCSI_PMC2)
# define SCSI_BASE_ADRS (CPU_PCI_IO_ADRS + PMC2_DEV_SPACE)
#else
# define SCSI_BASE_ADRS (CPU_PCI_IO_ADRS + SCSI_DEV_SPACE)
#endif /* defined (INCLUDE_SCSI_PMC) */
#endif /* !defined (INCLUDE_PCI_AUTOCONF) */
/* Additional PCI memory defines */
/*
* Macro to translate a PCI memory address to a local address as seen by the cpu
*/
#define PCI2CPU_PCI_MEM_ADRS(x) \
TRANSLATE(x, PCI_MSTR_MEMIO_BUS, PCI_MSTR_MEMIO_LOCAL)
/*
* Macro to translate a PCI ISA I/O address to a local address as seen by the cpu
*/
#define PCI2CPU_PCI_ISA_IO_ADRS(x) \
TRANSLATE(x, PCI_MSTR_ISA_IO_BUS, PCI_MSTR_ISA_IO_LOCAL)
/*
* Macro to translate a PCI I/O address to a local address as seen by the cpu
*/
#define PCI2CPU_PCI_IO_ADRS(x) \
TRANSLATE(x, PCI_MSTR_IO_BUS, PCI_MSTR_IO_LOCAL)
/*
* Macro to translate a local address to a PCI memory address
*/
#define CPU2PCI_PCI_MEM_ADRS(x) \
TRANSLATE(x, PCI_MSTR_MEMIO_LOCAL, PCI_MSTR_MEMIO_BUS)
/*
* Macro to translate a local address to a PCI I/O address
*/
#define CPU2PCI_PCI_IO_ADRS(x) \
TRANSLATE(x, PCI_MSTR_ISA_IO_LOCAL, PCI_MSTR_ISA_IO_BUS)
/* ISA IO device addresses */
#define ISA_INTR_ACK_REG (CPU_PCI_IACK_ADRS + 0x1ff0)
/* EPIC configuration defines */
#define EPIC_BASE_ADRS (CPU_EUMB_ADRS+0x40000)
#define EPIC_REG_SIZE 0x00040000
/* I2C configuration defines */
#define I2C_BASE_ADRS (CPU_EUMB_ADRS+0x03000)
#define I2C_REG_SIZE 0x00001000
/* Real Time Clock Dallas DS12885 */
#define ds12885_IDX_PORT (CPU_PCI_ISA_IO_ADRS + 0x0070)
#define ds12885_DATA_PORT (CPU_PCI_ISA_IO_ADRS + 0x0071)
/* z8536 aux timer and I/O chip */
#define z8536_PORTC_DATA (CPU_PCI_ISA_IO_ADRS + 0x0108)
#define z8536_PORTB_DATA (CPU_PCI_ISA_IO_ADRS + 0x0109)
#define z8536_PORTA_DATA (CPU_PCI_ISA_IO_ADRS + 0x010A)
#define z8536_PORT_CTRL (CPU_PCI_ISA_IO_ADRS + 0x010B)
#define ZCIO_CNTRL_ADRS (UINT8 *)(CPU_PCI_ISA_IO_ADRS + 0x10B)
#define ZCIO_IACK_ADRS (UINT8 *)(CPU_PCI_ISA_IO_ADRS + 0x10E)
#define CIO_RESET_DELAY 5000
#define CIO_INT_VEC Z8536_INT_LVL
#define ZERO 0
#define ZCIO_HZ 3000000 /* 3.0 MHz clock */
/* Lock register */
#define VG4_PORT_LOCKR (CPU_PCI_ISA_IO_ADRS + 0x0169)
#define LOCKR_LOCK 0x04 /* Lock Extended Registers (write access) */
#define LOCKR_UNLOCK 0x05 /* UnLock Extended Registers (write access) */
#define LOCKR_UNLOCKED 0xF8 /* Extended Registers is Unlocked (read access) */
#define LOCKR_LOCKED 0xFF /* Extended Registers is Locked (read access) */
/* Watchdog register */
#define VG4_PORT_WCR (CPU_PCI_ISA_IO_ADRS + 0x0160)
#define WCR_WD_ON 0x01 /* enable watchdog */
#define WCR_WD_OFF 0x00 /* disable watchdog */
#define WCR_WD_SET 0x02 /* set watchdog output line */
#define WCR_WD_RES 0x04 /* write: reset watchdog output line */
#define WCR_WD_REL 0x04 /* read: state of watchdog output line */
/* MCP ticker control register */
#define VG4_PORT_MCPTCR (CPU_PCI_ISA_IO_ADRS + 0x0161)
#define MCP_DIS 0x00 /* disable MCP timer */
#define MCP_0_286_MS 0x01 /* select 0.286 ms for MCP timer */
#define MCP_0_572_MS 0x02 /* select 0.572 ms for MCP timer */
#define MCP_1_144_MS 0x03 /* select 1.144 ms for MCP timer */
#define MCP_2_289_MS 0x04 /* select 2.289 ms for MCP timer */
#define MCP_4_577_MS 0x05 /* select 4.577 ms for MCP timer */
#define MCP_9_154_MS 0x06 /* select 9.154 ms for MCP timer */
#define MCP_18_309_MS 0x07 /* select 18.309 ms for MCP timer */
/* Card Fail LED control register */
#define VG4_PORT_LEDCR (CPU_PCI_ISA_IO_ADRS + 0x0168)
#define LEDCR_LED_ON 0x01 /* turn LED on */
#define LEDCR_LED_OFF 0x00 /* turn LED off */
#define WRONG_CPU_MSG "Wrong cpu type (%s) for this VxWorks image!\r\n";
/* CPU type */
#define CPU_TYPE ((vxPvrGet() >> 16) & 0xffff)
#define CPU_REV (vxPvrGet() & 0xffff)
#define CPU_TYPE_750 0x08 /* MPC750 CPU */
#define CPU_TYPE_7400 0x0C /* MPC7400 CPU */
#define CPU_TYPE_7410 0x800C /* MPC7410 CPU */
#define CPU_REV_750 0x0100 /* Processor revisions start at 0x0100 */
#define CPU_REV_755 0x3100 /* Processor revisions start at 0x3100, */
/* MPC755 (Goldfinger) has the same */
/* processor version (0x0008) as MPC750 */
#define CPU_REV_750_IBM 0x8000 /* Processor revisions start at 0x8000, */
/* IBM 750 PowerPC processors hav the */
/* same processor version (0x0008) as */
/* BSP configuration error policy */
#define CONTINUE_EXECUTION 0 /* Tolerate VPD/Configuration errors */
#define EXIT_TO_SYSTEM_MONITOR 1 /* Transfer to System Monitor */
/* Memory speed macro */
#if FALSE
# define MEMORY_BUS_SPEED 66666000 /* 66 MHz */
#else
# define MEMORY_BUS_SPEED 100000000 /* 100 MHz */
#endif
/* PPC Decrementer - used as vxWorks system clock */
#define DELTA(a,b) (abs((int)a - (int)b))
/* System clock (decrementer counter) frequency determination */
#define DEC_CLOCK_FREQ MEMORY_BUS_SPEED
/*
* The PowerPC Decrementer is used as the system clock.
* It is always included in this BSP. The following defines
* are used by the system clock library.
*/
#define SYS_CLK_RATE_MIN 10 /* minimum system clock rate */
#define SYS_CLK_RATE_MAX 5000 /* maximum system clock rate */
/*
* Auxiliary Clock support is an optional feature that is not supported
* by all BSPs. The following defines are used by the aux clock library.
*/
#define AUX_CLK_RATE_MIN 50 /* min auxiliary clock */
#define AUX_CLK_RATE_MAX 6000 /* max auxiliary clock rate */
/*
* Timestamp timer
*
* One of the four EPIC timers in the northbridge MPC107 may be used
* for the timestamp timer. To select one of these timers jfor timestamp
* define INCLUDE_EPIC_TIMESTAMP in config.h
*
* The default values for the timestamp timer are the maximum values for
* the EPIC timers.
*/
#define TIMESTAMP_PERIOD 0x7fffffff
#define TIMESTAMP_HZ 12500000 /* SDRAM frequency / 8 = 12.5 MHz */
/* M1543C Registers */
#define PCI_DEV_NO_M1543C 0x0012
#define M1543C_VEND_ID_REG 0x00
#define M1543C_DEV_ID_REG 0x02
#define M1543C_PCI_CMD 0x04
#define M1543C_PCI_STAT 0x06
#define M1543C_DEV_REV 0x08
#define M1543C_PIC 0x40
#define M1543C_IORC 0x41
#define M1543C_ISAC1 0x42
#define M1543C_ISAC2 0x43
#define M1543C_BCSC 0x47
#define M1543C_PIRT1 0x48
#define M1543C_PIRT2 0x49
#define M1543C_PIRT3 0x4A
#define M1543C_PIRT4 0x4B
#define M1543C_PILET 0x4C
#define M1543C_PCSAD 0x55
#define M1543C_GPIS 0x59 /* General Purpose Input (GPI) Multiplexed Pin Select */
#define M1543C_GPOS 0x5A /* General Purpose Output (GPO) Multiplexed Pin Select */
#define M1543C_DMDC 0x5C /* Docking Mode Decode Control */
#define M1543C_SMCCI 0x5E /* Suspend Mode Clock Control I */
#define M1543C_SMCCII 0x5F /* Suspend Mode Clock Control II */
/* M1543C PMU Registers */
#define PCI_DEV_NO_M1543C_PMU 0x1C
#define M1543C_PMU_EESS 0x4C /* Enable of External Switch SMI*/
#define M1543C_PMU_SESS 0x4E /* Status of External Switch SMI*/
#define M1543C_PMU_SMICNTL 0x77 /* SMI Control Register */
#define M1543C_PMU_COESI 0x80 /* Control of External Switch I (LM75 O.S. output ) */
#define M1543C_PMU_COESII 0x8C /* Control of External Switch II (boot select jumper) */
#define M1543C_PMU_LEDC 0xB5 /* LED Control Register */
#define M1543C_PMU_DOGPOI 0xC0 /* Data Output to GPO Pins */
#define M1543C_PMU_DOGPOII 0xC3 /* Data Output for GPO[23:22] */
#define M1543C_PMU_SMIRB 0xC6 /* Select Multifunctions in Resume Block */
/* M1543C Super I/O Registers */
#define M1543C_SIO_CNF_PORT 0x3F0
#define M1543C_SIO_IDX_PORT 0x3F0
#define M1543C_SIO_DATA_PORT 0x3F1
#define M1543C_SIO_RESET 0x02 /* Reset configuration register */
#define M1543C_SIO_LUN_IDX 0x07 /* Logical device select register */
#define M1543C_SIO_DEV_VER 0x1F /* ALI defined device revision */
#define M1543C_SIO_DEV_ID2 0x20 /* ALI define device identification */
#define M1543C_SIO_DEV_ID1 0x21 /* ALI define device identification */
#define M1543C_SIO_DPDR 0x22 /* Direct powerdown register */
#define M1543C_SIO_APDR 0x23 /* Auto powerdown register */
#define M1543C_SIO_ENR 0x30 /* Device enable register */
#define M1543C_SIO_HIAR 0x60 /* I/O high address register */
#define M1543C_SIO_LOAR 0x61 /* I/O low address register */
#define M1543C_SIO_IRQR 0x70 /* Device irq channel register */
#define M1543C_SIO_DMAR 0x74 /* Device dma channel register */
#define M1543C_SIO_CNFR 0xf0 /* Device configuration register 1 */
#define M1543C_SIO_CNF2R 0xf1 /* Device configuration register 2 */
#define M1543C_SIO_LUN_ENABLE 0x01 /* Logical device enable */
#define M1543C_SIO_LUN_DISABLE 0x00 /* Logical device disable */
/* M1543C Super I/O logical device numbers */
#define M1543C_SIO_LUN_FDC 0x00 /* floppy disk */
#define M1543C_SIO_LUN_LPT 0x03 /* LPT port */
#define M1543C_SIO_LUN_COM1 0x04 /* UART1 */
#define M1543C_SIO_LUN_COM2 0x05 /* UART3 */
#define M1543C_SIO_LUN_KBC 0x07 /* keyboard */
#define M1543C_SIO_LUN_UART3 0x0b /* UART 3 */
#define M1543C_SIO_LUN_HOTK 0x0c /* HOTK 3 */
/* M1543C Super I/O logical device */
#define M1543C_FDC_IO_ADRS (CPU_PCI_ISA_IO_ADRS + 0x03f0) /* floppy */
#define M1543C_LPT_IO_ADRS (CPU_PCI_ISA_IO_ADRS + 0x03bc) /* lpt */
#define M1543C_COM1_IO_ADRS (CPU_PCI_ISA_IO_ADRS + 0x03f8) /* com1 */
#define M1543C_COM2_IO_ADRS (CPU_PCI_ISA_IO_ADRS + 0x02f8) /* com2 */
/* DMA DEFINES */
#define M1543C_FDC_DMA 0x02
#define M1543C_LPT_DMA 0x03
/*
* UNIVERSE REGISTER SETUP FOR CPU <-> VME MAPPING (via PCI)
*
* ALL VAL_LSIx and VAL_VSIx values MUST be multiples of 64KB !!!
* Except VAL_LSI0 and VAL_VSI0, which must be multiples of 4KB !
*/
/*
* Defines for the VME MASTER WINDOWS
*/
/*
* VME MASTER WINDOW 0 is not used at the moment!
*
* VME MASTER WINDOW FOR LM/SEM (MAILBOX) REGISTERS
*
* Universe PCI slave (VME master) window 0
*
* Map access to A32 VMEbus (VME LM/SEM Regs) (64K)
*/
#define VME_A32_REG_SIZE 0x00001000 /* individual reg space */
#define VME_A32_REG_SPACE 0x00010000 /* total reg space */
#define VME_LM_SLV_SIZE VME_A32_REG_SIZE /* this boards reg space 4KB */
#define VME_LM_MSTR_SIZE VME_A32_REG_SPACE /* total system reg space 64KB*/
#if defined (ADRS_MAP_PREP)
/*
* Map access to A32 VMEbus (LM Regs) - 64K MAP for PReP vxWorks
* This maps: MPU RANGE: 0xf0000000 - 0xf000ffff
* to: PCI RANGE: 0x30000000 - 0x3000ffff
* to: VME RANGE: 0x40000000 - 0x4000ffff
*/
# define CPU_VME_WINDOW_REG_BASE 0xf0000000
# define VME_A32_REG_BASE 0x40000000
# define VME_LM_MSTR_LOCAL CPU_VME_WINDOW_REG_BASE
# define VME_LM_MSTR_BUS VME_A32_REG_BASE
# define VAL_LSI0_BS_VALUE (CPU_VME_WINDOW_REG_BASE - PCI_MSTR_MEMIO_LOCAL)
#else /* if defined (ADRS_MAP_PREP) */
/*
* Map access to A32 VMEbus (LM/SEM Regs) - 64K MAP for CHRP vxWorks
* This maps: MPU RANGE: 0xfcff0000 - 0xfcffffff
* to: PCI RANGE: 0xfcff0000 - 0xfcffffff
* to: VME RANGE: 0xfcff0000 - 0xfcffffff
*/
# define CPU_VME_WINDOW_REG_BASE 0xfcff0000
# define VME_A32_REG_BASE 0xfcff0000
# define VME_LM_MSTR_LOCAL CPU_VME_WINDOW_REG_BASE
# define VME_LM_MSTR_BUS VME_A32_REG_BASE
# define VAL_LSI0_BS_VALUE VME_LM_MSTR_LOCAL
#endif /* if defined (ADRS_MAP_PREP) */
#define VAL_LSI0_BS (VAL_LSI0_BS_VALUE)
#define VAL_LSI0_BD (VAL_LSI0_BS + VME_LM_MSTR_SIZE)
#define VAL_LSI0_TO (VME_LM_MSTR_BUS - VAL_LSI0_BS)
#define VAL_LSI0_CTL (LSI_CTL_EN | LSI_CTL_WP |\
LSI_CTL_D64 | LSI_CTL_A32 |\
LSI_CTL_DATA | LSI_CTL_USR |\
LSI_CTL_SINGLE | LSI_CTL_PCI_MEM)
/*
* VME MASTER WINDOW FOR A24 SPACE
*
* Universe PCI slave (VME master) window 2
*/
#if defined (ADRS_MAP_PREP)
/*
* Map access to A24 VMEbus - 16M MAP for PReP vxWorks
* This maps: MPU RANGE: 0xe0000000 - 0xe0ffffff
* to: PCI RANGE: 0x20000000 - 0x20ffffff
* to: VME RANGE: 0xff000000 - 0xffffffff
*/
# define VME_A24_MSTR_LOCAL 0xe0000000
#else /* defined (ADRS_MAP_PREP) */
/*
* Map access to A24 VMEbus - 16M MAP for CHRP vxWorks
* This maps: MPU RANGE: 0xfb000000 - 0xfbffffff
* to: PCI RANGE: 0xfb000000 - 0xfbffffff
* to: VME RANGE: 0xff000000 - 0xffffffff
*/
# define VME_A24_MSTR_LOCAL 0xfb000000
#endif /* defined (ADRS_MAP_PREP) */
#define VAL_LSI2_BS_VALUE (TRANSLATE(VME_A24_MSTR_LOCAL, PCI_MSTR_MEMIO_LOCAL, PCI_MSTR_MEMIO_BUS))
#if ((VME_A32_MSTR_LOCAL + VME_A32_MSTR_SIZE) > VME_A24_MSTR_LOCAL)
# error VME A32 space extends into the A24 memory space
#endif
#if (VME_A24_MSTR_SIZE > 0x01000000)
# error Maximum VME_A24_MSTR_SIZE cannot exceed 16 MB
#endif
#define VAL_LSI2_BS (VAL_LSI2_BS_VALUE)
#define VAL_LSI2_BD (VAL_LSI2_BS + VME_A24_MSTR_SIZE)
#define VAL_LSI2_TO (0xff000000 + VME_A24_MSTR_BUS - VAL_LSI2_BS)
#define VAL_LSI2_CTL (LSI_CTL_EN | LSI_CTL_WP |\
LSI_CTL_D16 | LSI_CTL_A24 |\
LSI_CTL_DATA | LSI_CTL_USR |\
LSI_CTL_SINGLE | LSI_CTL_PCI_MEM)
/*
* VME MASTER WINDOW FOR A32 SPACE
*
* Universe PCI slave (VME master) window 1
*/
#if defined (ADRS_MAP_PREP)
/*
* Map access to A32 VMEbus - 128M MAP for PReP vxWorks
* This maps: MPU RANGE: 0xd8000000 - 0xdfffffff
* to: PCI RANGE: 0x18000000 - 0x1fffffff
* to: VME RANGE: VME_A32_MSTR_BUS - VME_A32_MSTR_BUS + VME_A32_MSTR_SIZE
*/
# define VME_A32_MSTR_LOCAL 0xd8000000
# if (VME_A32_MSTR_SIZE > 0x08000000)
# error VME_A32_MSTR_SIZE cannot exceed 128 MB
# endif
#else /* defined (ADRS_MAP_PREP) */
/*
* Map access to A32 VMEbus - 1GB MAP for CHRP vxWorks
* This maps: MPU RANGE: 0xb0000000 - 0xefffffff
* to: PCI RANGE: 0xb0000000 - 0xefffffff
* to: VME RANGE: VME_A32_MSTR_BUS - VME_A32_MSTR_BUS + VME_A32_MSTR_SIZE
*/
# define VME_A32_MSTR_LOCAL 0xb0000000
#endif /* defined (ADRS_MAP_PREP) */
#define VAL_LSI1_BS_VALUE (TRANSLATE(VME_A32_MSTR_LOCAL, PCI_MSTR_MEMIO_LOCAL, PCI_MSTR_MEMIO_BUS))
#define VAL_LSI1_BS (VAL_LSI1_BS_VALUE)
#define VAL_LSI1_BD (VAL_LSI1_BS + VME_A32_MSTR_SIZE)
#define VAL_LSI1_TO (VME_A32_MSTR_BUS - VAL_LSI1_BS)
#define VAL_LSI1_CTL (LSI_CTL_EN | LSI_CTL_WP |\
LSI_CTL_D64 | LSI_CTL_A32 |\
LSI_CTL_DATA | LSI_CTL_USR |\
LSI_CTL_SINGLE | LSI_CTL_PCI_MEM)
/*
* VME MASTER WINDOW FOR A16 SPACE
*
* Universe PCI slave (VME master) window 3
*/
#if defined (ADRS_MAP_PREP)
/*
* Map access to A16 VMEbus - 64K MAP for PReP vxWorks
* This maps: MPU RANGE: 0xefff0000 - 0xefffffff
* to: PCI RANGE: 0x2fff0000 - 0x2fffffff
* to: VME RANGE: 0xffff0000 - 0xffffffff
*/
# define VME_A16_MSTR_LOCAL 0xefff0000
#else /* defined (ADRS_MAP_PREP) */
/*
* Map access to A16 VMEbus - 64K MAP for CHRP vxWorks
* This maps: MPU RANGE: 0xfcfe0000 - 0xfcfeffff
* to: PCI RANGE: 0xfcfe0000 - 0xfcfeffff
* to: VME RANGE: 0xfcfe0000 - 0xfcfeffff
*/
# define VME_A16_MSTR_LOCAL 0xfcfe0000
#endif /* defined (ADRS_MAP_PREP) */
#define VAL_LSI3_BS_VALUE (TRANSLATE(VME_A16_MSTR_LOCAL, PCI_MSTR_MEMIO_LOCAL, PCI_MSTR_MEMIO_BUS))
#if (VME_A16_MSTR_SIZE > 0x00010000)
# error Maximum VME_A16_MSTR_SIZE cannot exceed 64 KB
#endif
#define VME_A16_MSTR_BUS 0x00000000 /* must be 0 */
#define VAL_LSI3_BS (VAL_LSI3_BS_VALUE)
#define VAL_LSI3_BD (VAL_LSI3_BS + VME_A16_MSTR_SIZE)
#define VAL_LSI3_TO (0xffff0000 + VME_A16_MSTR_BUS - VAL_LSI3_BS)
#define VAL_LSI3_CTL (LSI_CTL_EN | LSI_CTL_WP |\
LSI_CTL_D16 | LSI_CTL_A16 |\
LSI_CTL_DATA | LSI_CTL_USR |\
LSI_CTL_SINGLE | LSI_CTL_PCI_MEM)
/*
* VME MASTER MEMORY WINDOW LIMITS
*
* These values are strictly defined by the base memory addresses and window
* sizes of the spaces defined above. These values must be correct for the
* sysBusProbe() memory range checks of the VME bus to work properly.
*/
#define VME_MSTR_LO_ADRS (VME_A32_MSTR_LOCAL)
#if defined (ADRS_MAP_PREP)
# define VME_MSTR_HI_ADRS (VME_LM_MSTR_LOCAL + VME_LM_MSTR_SIZE)
#else /* defined (ADRS_MAP_PREP) */
# if FALSE
# define VME_MSTR_HI_ADRS (VME_LM_MSTR_LOCAL + VME_LM_MSTR_SIZE)
# else
# define VME_MSTR_HI_ADRS (VME_A16_MSTR_LOCAL + VME_A16_MSTR_SIZE)
# endif
#endif /* defined (ADRS_MAP_PREP) */
/*
* Defines for the VME SLAVE WINDOWS
*
* Allows for the decoding of addresses on the VMEbus.
*/
/*
* VME SLAVE WINDOW 0 is not used at the moment!
*
* VME SLAVE WINDOW FOR REG SPACE
*
* Universe VME slave window 0.
*
* Setup to access the node's VME LM/SEM Regs via
* A32 space on VMEbus (4KB)
* This range needs to be unique for each target board.
*/
/*
* MAP FOR STANDARD vxWorks
* This maps: VME RANGE: (0x40000000 + (0x1000 * ProcNum)) -
* (0x40000fff + (0x1000 * ProcNum))
* to: PCI RANGE: 0x00001000 - 0x00001fff - ISA I/O Space
*/
#define VAL_VSI0_TO_VALUE (0xc0001000 - (sysProcNumGet() * \
VME_A32_REG_SIZE))
#define VAL_VSI0_BS (VME_A32_REG_BASE + (sysProcNumGet() * \
VME_A32_REG_SIZE))
#define VAL_VSI0_BD (VME_A32_REG_BASE + ((sysProcNumGet() + 1) * \
VME_A32_REG_SIZE))
#define VAL_VSI0_TO (VAL_VSI0_TO_VALUE)
#define VAL_VSI0_CTL (VSI_CTL_EN | \
VSI_CTL_AM_DATA | VSI_CTL_AM_PGM |\
VSI_CTL_AM_SUPER | VSI_CTL_AM_USER |\
VSI_CTL_VAS_A32 | VSI_CTL_LAS_IO )
/*
* VME SLAVE WINDOW FOR A32 SPACE
*
* Universe VME slave window 1
*
* VME bus A32 window to access the master node's local memory.
* This VME Slave window is only used by the master node.
*
* vxWorks PReP Map
* This maps: VME RANGE: 0x08000000 - (0x08000000 + VME_A32_SLV_SIZE - 1)
* to: PCI RANGE: 0x80000000 - 0x80000000 + VME_A32_SLV_SIZE-1
* to: MPU RANGE: 0x00000000 - VME_A32_SLV_SIZE-1
*
* vxWorks CHRP Map
* This maps: VME RANGE: 0x00000000 - (0x00000000 + VME_A32_SLV_SIZE - 1)
* to: PCI RANGE: 0x00000000 - VME_A32_SLV_SIZE-1
* to: MPU RANGE: 0x00000000 - VME_A32_SLV_SIZE-1
*/
#define VAL_VSI1_BS (VME_A32_SLV_BUS)
#if (SM_OFF_BOARD == TRUE)
# define VAL_VSI1_BD (VAL_VSI1_BS + VME_A32_SLV_SIZE)
#else
# ifdef ANY_BRDS_IN_CHASSIS_NOT_RMW
# define VAL_VSI1_BD (VAL_VSI1_BS + VME_A32_SLV_SIZE)
# else
# define VAL_VSI1_BD (VAL_VSI1_BS + SM_MEM_ADRS)
# endif /* ANY_BRDS_IN_CHASSIS_NOT_RMW */
#endif /* SM_OFF_BOARD */
#define VAL_VSI1_TO (PCI_SLV_MEM_BUS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)
#define VAL_VSI1_CTL (VSI_CTL_EN | VSI_CTL_PREN | \
VSI_CTL_AM_DATA | VSI_CTL_AM_PGM | \
VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
VSI_CTL_VAS_A32 | VSI_CTL_LAS_MEM | \
VSI_CTL_LD64EN )
#if defined (A24_SLV_WINDOW)
/*
* VME SLAVE WINDOW FOR A24 SPACE
*
* Universe VME slave window 2
*
* VME bus A24 window to access the master node's local memory.
* This VME Slave window is only used by the master node.
*
* vxWorks PReP Map
* This maps: VME RANGE: 0x00000000 - (VME_A24_SLV_SIZE - 1)
* to: PCI RANGE: 0x80000000 - 0x80000000 + VME_A24_SLV_SIZE-1
* to: MPU RANGE: 0x00000000 - VME_A24_SLV_SIZE-1
*
* vxWorks CHRP Map
* This maps: VME RANGE: 0x00000000 - (VME_A24_SLV_SIZE - 1)
* to: PCI RANGE: 0x00000000 - VME_A24_SLV_SIZE-1
* to: MPU RANGE: 0x00000000 - VME_A24_SLV_SIZE-1
*/
# define VAL_VSI2_BS (VME_A24_SLV_BUS)
# define VAL_VSI2_BD (VAL_VSI2_BS + VME_A24_SLV_SIZE)
# define VAL_VSI2_TO (PCI_SLV_MEM_BUS - VAL_VSI2_BS + VME_A24_SLV_LOCAL)
# define VAL_VSI2_CTL (VSI_CTL_EN | VSI_CTL_PREN | \
VSI_CTL_AM_DATA | VSI_CTL_AM_PGM | \
VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
VSI_CTL_VAS_A24 | VSI_CTL_LAS_MEM | \
VSI_CTL_LD64EN )
#endif /* defined (A24_SLV_WINDOW) */
/* VSI4 and VSI5 are only applicable to the Universe II */
#define VAL_VSI4_BS (VAL_VSI1_BS + \
SM_MEM_ADRS)
#define VAL_VSI4_BD (VAL_VSI1_BS + \
SM_MEM_ADRS + \
SM_MEM_SIZE + \
SM_OBJ_MEM_SIZE)
#define VAL_VSI4_TO (PCI2DRAM_BASE_ADRS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)
#define VAL_VSI4_CTL ( VSI_CTL_EN | VSI_CTL_PREN | \
VSI_CTL_AM_DATA | VSI_CTL_AM_PGM | \
VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
VSI_CTL_VAS_A32 | VSI_CTL_LAS_MEM | \
VSI_CTL_LD64EN | VSI_CTL_PWEN | \
VSI_CTL_LLRMW )
#define VAL_VSI5_BS (VAL_VSI1_BS + \
SM_MEM_ADRS + \
SM_MEM_SIZE + \
SM_OBJ_MEM_SIZE)
#define VAL_VSI5_BD (VAL_VSI1_BS + VME_A32_SLV_SIZE)
#define VAL_VSI5_TO (PCI2DRAM_BASE_ADRS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)
#define VAL_VSI5_CTL ( VSI_CTL_EN | VSI_CTL_PREN | \
VSI_CTL_AM_DATA | VSI_CTL_AM_PGM | \
VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
VSI_CTL_VAS_A32 | VSI_CTL_LAS_MEM | \
VSI_CTL_LD64EN | VSI_CTL_PWEN )
/*
* VME SLAVE WINDOW FOR A16 SPACE
*
* Universe VME A16 Slave window, does not exist. (Could use window 3.)
*/
#define VME_A16_SLV_BUS 0x0
#define VME_A16_SLV_SIZE 0x0 /* 0, window is disabled */
#define VME_A16_SLV_LOCAL 0x0
/* defines for the UNIV II location monitor register space */
#define VAL_LM_CTL (LM_CTL_EN | LM_CTL_PGM_BOTH | \
LM_CTL_BOTH | LM_CTL_VAS_A32)
#define VAL_LM_BS (VME_LM_MSTR_BUS + (sysProcNumGet() * \
VME_LM_SLV_SIZE))
/* Universe Special Cycle Generator values */
#define VME_SCG_COMPARE_MASK 0xffffffff
#define VME_SCG_COMPARE_TO_SET 0x00000000
#define VME_SCG_SWAP_TO_SET 0x80000000
#define VME_SCG_COMPARE_TO_CLEAR 0x80000000
#define VME_SCG_SWAP_TO_CLEAR 0x00000000
/* INTERRUPT DEFINES */
#define M1543C_FDC_IRQ 0x06
#define M1543C_LPT_IRQ 0x07
#define M1543C_COM1_IRQ 0x04
#define M1543C_COM2_IRQ 0x03
#define M1543C_KBC_IRQ 0x01
#define ISA_INTERRUPT_BASE 0x00
#define EXT_INTERRUPT_BASE 0x10
#define TIMER_INTERRUPT_BASE 0x20
#define ERR_INTERRUPT_BASE 0x28
#define ESCC_INTERRUPT_BASE 0x00
/* PIB (8259) interrupt connection */
#define PIB_INT_LVL ( 0x00 + EXT_INTERRUPT_BASE )
/* ISA interrupt Level definitions */
/* programable timer interrupt level */
#define PIT_INT_LVL ( 0x00 + ISA_INTERRUPT_BASE )
/* keyboard interrupt level */
#define KBD_INT_LVL ( 0x01 + ISA_INTERRUPT_BASE )
/* com port 1 interrupt level */
#define COM1_INT_LVL ( M1543C_COM1_IRQ + ISA_INTERRUPT_BASE )
/* com port 2 interrupt level */
#define COM2_INT_LVL ( M1543C_COM2_IRQ + ISA_INTERRUPT_BASE )
/* level 5 */
/* floppy interrupt level */
#define FD_INT_LVL ( M1543C_FDC_IRQ + ISA_INTERRUPT_BASE )
/* Parallel port level */
#define PP_INT_LVL ( M1543C_LPT_IRQ + ISA_INTERRUPT_BASE )
/* RTC interrupt level */
#define RTC_INT_LVL ( 0x08 + ISA_INTERRUPT_BASE )
/* level 9 */
/* z85230 timer interrupt level */
#define Z85230_INT_LVL ( 0x0a + ISA_INTERRUPT_BASE )
/* z8536 timer interrupt level */
#define Z8536_INT_LVL ( 0x0b + ISA_INTERRUPT_BASE )
/* mouse interrupt level */
#define MOU_INT_LVL ( 0x0c + ISA_INTERRUPT_BASE )
/* level 13 */
/* USB interrupt level */
#define USB_INT_LVL ( 0x0f + ISA_INTERRUPT_BASE )
/* PCI interrupt levels */
/* PCI INTA# */
#define PCI_INTA_LVL ( 0x01 + EXT_INTERRUPT_BASE )
/* PCI INTB# */
#define PCI_INTB_LVL ( 0x02 + EXT_INTERRUPT_BASE )
/* PCI INTC# */
#define PCI_INTC_LVL ( 0x03 + EXT_INTERRUPT_BASE )
/* PCI INTD# */
#define PCI_INTD_LVL ( 0x04 + EXT_INTERRUPT_BASE )
/* PMC1 interrupt levels */
/* PMC1 INTA# */
#define PMC_INT_LVL1 PCI_INTD_LVL
/* PMC1 INTB# */
#define PMC_INT_LVL2 PCI_INTA_LVL
/* PMC1 INTC# */
#define PMC_INT_LVL3 PCI_INTB_LVL
/* PMC1 INTD# */
#define PMC_INT_LVL4 PCI_INTC_LVL
/* PMC2 interrupt levels */
/* PMC2 INTA# */
#define PMC2_INT_LVL1 PCI_INTC_LVL
/* PMC2 INTB# */
#define PMC2_INT_LVL2 PCI_INTD_LVL
/* PMC2 INTC# */
#define PMC2_INT_LVL3 PCI_INTA_LVL
/* PMC2 INTD# */
#define PMC2_INT_LVL4 PCI_INTB_LVL
/* ethernet interrupt level */
#define LN_INT_LVL PCI_INTA_LVL
/* universe interrupt level */
#define UNIV_INT_LVL PCI_INTB_LVL
/* SCSI interrupt level */
#if defined (INCLUDE_SCSI_PMC)
# define SCSI_INT_LVL PMC_INT_LVL1
#elif defined (INCLUDE_SCSI_PMC2)
# define SCSI_INT_LVL PMC2_INT_LVL1
#else
# define SCSI_INT_LVL PCI_INTC_LVL
#endif /* defined (INCLUDE_SCSI_PMC) */
/* universe mailbox interrupt */
#define LM_SIG_INT_LVL UNIV_INT_LVL
#define PIRQ0(irq) (irq << 12)
#define PIRQ1(irq) (irq << 8)
#define PIRQ2(irq) (irq << 4)
#define PIRQ3(irq) (irq)
/* EPIC timer interrupt levels */
#define EPIC_TIMER0_INT_LVL ( 0x00 + TIMER_INTERRUPT_BASE )
#define EPIC_TIMER1_INT_LVL ( 0x01 + TIMER_INTERRUPT_BASE )
#define EPIC_TIMER2_INT_LVL ( 0x02 + TIMER_INTERRUPT_BASE )
#define EPIC_TIMER3_INT_LVL ( 0x03 + TIMER_INTERRUPT_BASE )
/* interrupt vector definitions */
#define INT_VEC_IRQ0 0x00 /* vector for IRQ0 */
/* ISA interrupt vectors */
#define PIT_INT_VEC (INT_VEC_IRQ0 + PIT_INT_LVL)
#define KBD_INT_VEC (INT_VEC_IRQ0 + COM2_INT_LVL)
#define COM2_INT_VEC (INT_VEC_IRQ0 + COM2_INT_LVL)
#define COM1_INT_VEC (INT_VEC_IRQ0 + COM1_INT_LVL)
#define FD_INT_VEC (INT_VEC_IRQ0 + FD_INT_LVL)
#define PP_INT_VEC (INT_VEC_IRQ0 + PP_INT_LVL)
#define RTC_INT_VEC (INT_VEC_IRQ0 + RTC_INT_LVL)
#define Z8536_INT_VEC (INT_VEC_IRQ0 + Z8536_INT_LVL)
#define Z85230_INT_VEC (INT_VEC_IRQ0 + Z85230_INT_LVL)
/* PCI/EPIC interrupt vectors */
#define LN_INT_VEC (INT_VEC_IRQ0 + LN_INT_LVL)
#define UNIV_INT_VEC (INT_VEC_IRQ0 + UNIV_INT_LVL)
#define SCSI_INT_VEC (INT_VEC_IRQ0 + SCSI_INT_LVL)
#define PIB_INT_VEC (INT_VEC_IRQ0 + PIB_INT_LVL)
#define PCI_INTA_VEC (INT_VEC_IRQ0 + PCI_INTA_LVL)
#define PCI_INTB_VEC (INT_VEC_IRQ0 + PCI_INTB_LVL)
#define PCI_INTC_VEC (INT_VEC_IRQ0 + PCI_INTC_LVL)
#define PCI_INTD_VEC (INT_VEC_IRQ0 + PCI_INTD_LVL)
#define PMC_INT_VEC1 (INT_VEC_IRQ0 + PMC_INT_LVL1)
#define PMC_INT_VEC2 (INT_VEC_IRQ0 + PMC_INT_LVL2)
#define PMC_INT_VEC3 (INT_VEC_IRQ0 + PMC_INT_LVL3)
#define PMC_INT_VEC4 (INT_VEC_IRQ0 + PMC_INT_LVL4)
#define PMC2_INT_VEC1 (INT_VEC_IRQ0 + PMC2_INT_LVL1)
#define PMC2_INT_VEC2 (INT_VEC_IRQ0 + PMC2_INT_LVL2)
#define PMC2_INT_VEC3 (INT_VEC_IRQ0 + PMC2_INT_LVL3)
#define PMC2_INT_VEC4 (INT_VEC_IRQ0 + PMC2_INT_LVL4)
/* UNIVERSE chip interrupt vector defines */
#define UNIV_DMA_INT_VEC 0x56
#define UNIV_VME_SW_IACK_INT_VEC 0x57
#define UNIV_PCI_SW_INT_VEC 0x58
#define UNIV_VOWN_INT_VEC 0x59
#define UNIV_LERR_INT_VEC 0x5a
#define UNIV_VERR_INT_VEC 0x5c
#define UNIV_SYSFAIL_INT_VEC 0x5d
#define UNIV_ACFAIL_INT_VEC 0x5f
#define UNIV_MBOX0_INT_VEC 0x60 /* Mailbox 0 interrupt vector */
#define UNIV_MBOX1_INT_VEC 0x61 /* Mailbox 1 interrupt vector */
#define UNIV_MBOX2_INT_VEC 0x62 /* Mailbox 2 interrupt vector */
#define UNIV_MBOX3_INT_VEC 0x63 /* Mailbox 3 interrupt vector */
#define UNIV_LM0_INT_VEC 0x64 /* Loc. Mon. 0 interrupt vec. */
#define UNIV_LM1_INT_VEC 0x65 /* Loc. Mon. 1 interrupt vec. */
#define UNIV_LM2_INT_VEC 0x66 /* Loc. Mon. 2 interrupt vec. */
#define UNIV_LM3_INT_VEC 0x67 /* Loc. Mon. 3 interrupt vec. */
/* EPIC timer interrupt vectors */
#define EPIC_TIMER0_INT_VEC (INT_VEC_IRQ0 + EPIC_TIMER0_INT_LVL)
#define EPIC_TIMER1_INT_VEC (INT_VEC_IRQ0 + EPIC_TIMER1_INT_LVL)
#define EPIC_TIMER2_INT_VEC (INT_VEC_IRQ0 + EPIC_TIMER2_INT_LVL)
#define EPIC_TIMER3_INT_VEC (INT_VEC_IRQ0 + EPIC_TIMER3_INT_LVL)
/* EPIC timer interrupt priorities */
#define EPIC_TIMER0_PRIORITY PRIORITY_LVL15
#define EPIC_TIMER1_PRIORITY PRIORITY_LVL14
#define EPIC_TIMER2_PRIORITY PRIORITY_LVL13
#define EPIC_TIMER3_PRIORITY PRIORITY_LVL12
/*
* Address range definitions for VME and PCI buses.
*
* Used with vxMemProbe() hook sysBusProbe().
*/
#define IS_VME_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)VME_MSTR_LO_ADRS) && \
((UINT32)(adrs) < (UINT32)VME_MSTR_HI_ADRS))
#define IS_PCI_IO_ADDRESS(adrs) \
((((UINT32)(adrs) >= (UINT32)PCI_MSTR_ISA_IO_LOCAL) && \
((UINT32)(adrs) < (UINT32)(PCI_MSTR_ISA_IO_LOCAL + \
PCI_MSTR_ISA_IO_SIZE))) || \
(((UINT32)(adrs) >= (UINT32)PCI_MSTR_IO_LOCAL) && \
((UINT32)(adrs) < (UINT32)(PCI_MSTR_IO_LOCAL + \
PCI_MSTR_IO_SIZE))))
#define IS_PCI_MEM_ADDRESS(adrs) \
((((UINT32)(adrs) >= (UINT32)PCI_MSTR_ISA_MEM_LOCAL) && \
((UINT32)(adrs) < (UINT32)(PCI_MSTR_ISA_MEM_LOCAL + \
PCI_MSTR_ISA_MEM_SIZE))) ||\
(((UINT32)(adrs) >= (UINT32)PCI_MSTR_MEMIO_LOCAL) && \
((UINT32)(adrs) < (UINT32)(PCI_MSTR_MEM_LOCAL + \
PCI_MSTR_MEM_SIZE))))
#define IS_PCI_ADDRESS(adrs) \
(IS_PCI_MEM_ADDRESS(adrs) || \
IS_PCI_IO_ADDRESS(adrs))
/* VME Interrupt Bit definitions */
#define SIG1_INTR_SET 0x80
#define SIG0_INTR_SET 0x40
#define LM1_INTR_SET 0x20
#define LM0_INTR_SET 0x10
#define SIG1_INTR_CLEAR 0x08
#define SIG0_INTR_CLEAR 0x04
#define LM1_INTR_CLEAR 0x02
#define LM0_INTR_CLEAR 0x01
#define SIG1_INTR_ENABL 0x80
#define SIG0_INTR_ENABL 0x40
#define LM1_INTR_ENABL 0x20
#define LM0_INTR_ENABL 0x10
#define SIG1_INTR_STATUS 0x08
#define SIG0_INTR_STATUS 0x04
#define LM1_INTR_STATUS 0x02
#define LM0_INTR_STATUS 0x01
/* PCI bus number for primary PCI bus */
#define PCI_PRIMARY_BUS 0
/* macros for alignment */
#define REG_BASE(reg) (reg&~0x3)
#define REG_OFF(reg) (reg&0x3)
#define HI_ADR(adr) ((adr>>8)&0xff)
#define LO_ADR(adr) (adr&0xff)
/* programmable interrupt controller (PIC) */
#define PIC1_BASE_ADR M1543C_INT1_CTRL
#define PIC2_BASE_ADR M1543C_INT2_CTRL
#define PIC_REG_ADDR_INTERVAL 1 /* address diff of adjacent regs. */
/* serial ports (COM1 - COM2) */
#ifdef INCLUDE_NS16550_SIO
# define COM1_BASE_ADR M1543C_COM1_IO_ADRS /* serial port 1 */
# define COM2_BASE_ADR M1543C_COM2_IO_ADRS /* serial port 2 */
# define UART_REG_ADDR_INTERVAL 1 /* addr diff of adjacent regs */
# define N_UART_CHANNELS 2 /* No. serial I/O channels */
# define UART_BAUD_CLK_FREQ ((UINT32)0x1C2B89) /* 24MHz/13 */
# define UART_BAUD_DEFAULT 9600 /* default baud rate */
#endif /* INCLUDE_NS16550_SIO */
/* serial ports (COM3 - COM4) */
/*
* #ifdef INCLUDE_Z85230_SIO
*/
# define COM3_BASE_ADR z85230_PORTA_CTRL /* serial port 3 */
# define COM4_BASE_ADR z85230_PORTA_CTRL /* serial port 4 */
# define BAUD_CLK_FREQ 20000000 /* 20 MHz "P Clock" (fixed) */
# undef DATA_REG_85230_DIRECT
# define COM3_DTR_MASK 0x01
# define COM3_DSR_MASK 0x02
# define COM4_DTR_MASK 0x10
# define COM4_DSR_MASK 0x20
/*
* #endif /@ INCLUDE_Z85230_SIO @/
*/
/* total number of serial ports */
#if defined(INCLUDE_NS16550_SIO) && defined(INCLUDE_Z85230_SIO)
# define N_SIO_CHANNELS 4 /* No. serial I/O channels */
#elif defined(INCLUDE_NS16550_SIO)
# define N_SIO_CHANNELS 2 /* No. serial I/O channels */
#elif defined(INCLUDE_Z85230_SIO)
# define N_SIO_CHANNELS 2 /* No. serial I/O channels */
#else
# define N_SIO_CHANNELS 0 /* No. serial I/O channels */
#endif
/* select Z85230 port A and/or B. Adjust according to N_SIO_CHANNELS */
#ifdef INCLUDE_Z85230_SIO
# define Z85230_SIO_A
# define Z85230_SIO_B
#endif
/* parallel port (LPT1) */
#define PP_IO_ADRS M1543C_LPT_IO_ADRS
#define LPT_CHANNELS 1
/* Extended Intel Flash */
#define INTEL_FLASH_64_BIT
/* Settings for User LED (M1543C_PMU_LEDC register) */
#define VG4_USR_LED_MSK 0x03
#define VG4_USR_LED_ON 0x00
#define VG4_USR_LED_OFF 0x01
#define VG4_USR_LED_TOGGLE_1 0x02
#define VG4_USR_LED_TOGGLE_2 0x03
/*
* Support for determining if we're ROM based or not.
*/
#define PCI_AUTOCONFIG_FLAG_OFFSET ( 0x4c00 )
#define PCI_AUTOCONFIG_FLAG ( *(UCHAR *)(LOCAL_MEM_LOCAL_ADRS + \
PCI_AUTOCONFIG_FLAG_OFFSET) )
#define PCI_AUTOCONFIG_DONE ( PCI_AUTOCONFIG_FLAG != 0 )
/*
* I2C bus device addresses
*/
#define I2C_USR_EEPROM_ADRS 0xA8
#define I2C_SPD_EEPROM_ADRS 0xA0
#define I2C_LM75_ADRS 0x9E
/*
* Board Type Keys
*/
#define BOARDKEY_POS_CPU 3
#define BOARDKEY_POS_MEM 4
#define BOARDKEY_POS_FLASH 5
#define BOARDKEY_POS_LAN 6
#define BOARDKEY_POS_SCSI 7
#define BOARDKEY_POS_1553 8
#define BOARDKEY_POS_COM34 9
#define BOARDKEY_POS_LPT 10
#define BOARDKEY_POS_STYLE 11
#define BOARDKEY_MAXLEN 0x10
/* COM1..4 configuration options */
#define BOARDKEY_COM34_NP '0' /* COM3/4 not populated */
#define BOARDKEY_COM34_422 '1' /* COM3 and COM4 = rs422/485 */
#define BOARDKEY_COM34_232_422 '2' /* COM3 = rs232, COM4 = rs422/485 */
#define BOARDKEY_COM34_232 '3' /* COM3 and COM4 = rs232 */
#define BOARDKEY_COM1234_422T '4' /* COM1, COM2, COM3 and COM4 = rs422 terminated */
/*
* Create a single macro INCLUDE_MMU
*/
#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
# define INCLUDE_MMU
#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */
/*
* Enforce some INCLUDE's which are not optional to the user.
*/
#ifdef INCLUDE_MMU_FULL /* Full overrides basic */
# undef INCLUDE_MMU_BASIC
#endif /* INCLUDE_MMU_FULL */
#ifdef INCLUDE_NETWORK /* Network means PCI */
# ifndef INCLUDE_PCI
# define INCLUDE_PCI
# endif
#endif /* INCLUDE_NETWORK */
#ifdef __cplusplus
}
#endif
#endif /* INC_vg4_h */