www.pudn.com > vxworks0108.rar > sysL2BackCache.h
/* sysL2BackCache - defines registers and values for L2 cache control */
/*
DESCRIPTION
This file defines registers and values needed in defining l2 cache functions.
*/
#ifndef __INCsysL2BackCacheh
#define __INCsysL2BackCacheh
#ifdef __cplusplus
extern "C" {
#endif
#include "type.h"
#define L2CR_REG 1017 /* l2CR register number */
#define HID0_REG 1008
#define PVR_REG 287 /* pvr register number */
#define ARTHUR 8 /* Upper bit 16 bit value of 740/750 */
#define WRITE_ADDR_U 0x0060 /* upper 16 bits of write address */
#define L2_SIZE_1M_U 0x0010 /* upper 16 bitts of 1 Meg */
#define L2_ADR_INCR 0x100 /* address increament value */
#define L2_SIZE_1M 0x1000 /* 1 MG (0x100000) / 0x100 = 0x1000 */
#define L2_SIZE_HM 0x800 /* 512K counts */
#define L2_SIZE_QM 0x400 /* 256K(0x40000) / L2_ADR_INCR = 0x40 */
/*
* Defining values for L2CR register:
* - L2 cache enable (1) / disable (0) (bit 0)
* - cache size (bits 2-3; 3: 1 MB, 2: 512 KB, 1: 256 KB)
* - 1.5 clock ratio (bits 4-6)
* - Pinpelined (register-register) synchronous burst RAM (bits 7-8)
* - L2 Data only (bit 9)
* - Test mode on (1) or off (0) (bit 13)
*
*/
/* L2 Data Parity generation and checking enable */
#define L2CR_PE 0x4000
/* values for the L2SIZ bits */
#define L2CR_SIZE_2MB 0x0000
#define L2CR_SIZE_256KB 0x1000
#define L2CR_SIZE_512KB 0x2000
#define L2CR_SIZE_1MB 0x3000
#define L2_CACHE_SIZE L2CR_SIZE_1MB
/* values for L2CLK bits */
#define L2CR_CLK_DISABLE 0x0000
#define L2CR_CLK_1 0x0200
#define L2CR_CLK_1_5 0x0400
#define L2CR_CLK_3_5 0x0600
#define L2CR_CLK_2 0x0800
#define L2CR_CLK_2_5 0x0a00
#define L2CR_CLK_3 0x0c00
#define L2CR_CLK_4 0x0e00
/* values for L2RAM Type */
#define L2CR_RAM_SYNBRST 0x0000 /* synchronous burst SRAM */
#define L2CR_RAM_PB3 0x0080 /* PB3 synchronous burst SRAM (7xx)*/
#define L2CR_RAM_PB2 0x0100 /* PB2 synchronous burst SRAM */
#define L2CR_RAM_SYNLTWRT 0x0180 /* Synchronouus Late write SRAM */
/* L2 data only */
#define L2DO 0x0040
/* L2 Global invalidate */
#define L2CR_GBL_INV_U 0x0020
/* L2 Ram Control (ZZ enable) */
#define L2CR_RAMCTL 0x0010
/* L2 Write Through */
#define L2CR_WT 0x0008
/* L2 Test Support */
#define L2CR_TS 0x0004
/* L2 Output Hold */
#define L2CR_OH_0_5ns 0x0000
#define L2CR_OH_1_0ns 0x0001
#define L2CR_OH_MORE 0x0002
#define L2CR_OH_EVEN_MORE 0x0003
/* L2 Ins. only mode */
#define L2IO 0x0400
#define L2CR_CFG ( L2_CACHE_SIZE | \
L2CR_RAM_PB2 | \
L2CR_WT | \
L2CR_OH_0_5ns)
#define L2CR_DISABLE_MASK_U 0x7fff /* Disable L2 - upper 16 bits */
#define L2CR_EN_U 0x8000 /* Set L2CR enable bit */
#define L2CR_FA 0x1000 /* flush assist (software flush) */
#define L2CR_HWF 0x0800 /* hardware flush */
#define L2CR_IP 0x0001 /* Invalidation in progress */
#ifdef INCLUDE_L2PM
/* L2PM Register address */
#define L2PM_REG 1016
/* Base Address for the L2 Private Memory equivalent to mem size*/
#define L2PMBA ( L2PM_SRAM_ADRS >> 16 )
/* L2PM_SIz bit configration to determine the size of L2 private memeory */
#define L2PM_SIZE_256KB 0x0001
#define L2PM_SIZE_512KB 0x0002
#define L2PM_SIZE_1M 0x0003
#endif
#define L1_DCACHE_ENABLE 0x4400
#define L1_DCACHE_INV_MASK 0xfbff
#define L1_DCACHE_DISABLE 0xbfff
#ifndef _ASMLANGUAGE
extern void sysL1DcacheEnable(void);
extern void sysL2BackEnable(void);
extern ULONG sysL2BackAutoSize(void);
extern void sysL1DcacheDisable(void);
extern void sysL2BackDisable(void);
extern void sysL2BackGlobalInv(void);
extern void sysL2BackFlush(void);
extern void sysL2CRWrite(ULONG);
extern ULONG sysPVRReadBoot();
extern ULONG sysPVRReadSys();
extern ULONG sysL2CRRead();
extern void sysL2BackInit(void);
extern ULONG sysHID0READ(void);
extern ULONG sysHID0Write(ULONG);
#if defined(INCLUDE_L2PM) && defined(SP755)
extern void sysL2PMEnable();
#endif /* INCLUDE_L2PM && SP755 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* __INCsysL2BackCacheh */