www.pudn.com > vxworks0108.rar > reg.h
#ifndef _REG_H #define _REG_H /* register definition */ /* volatile registers that are not saved cross subroutine calls */ #define p0 r3 /* argument register, volatile */ #define p1 r4 /* argument register, volatile */ #define p2 r5 /* argument register, volatile */ #define p3 r6 /* argument register, volatile */ #define p4 r7 /* argument register, volatile */ #define p5 r8 /* argument register, volatile */ #define p6 r9 /* argument register, volatile */ #define p7 r10 /* argument register, volatile */ #define glr0 r0 /* prologs(PO,EABI), epilogs, glink routines(EABI) / * language specific purpose(SVR4), volatile */ #define glr1 r11 /* prologs, epilogs, as Pascal environment pointer(EABI) * language specific purpous (SVR4) * calls by pointer, as Pascal environment(PO), * volatile */ #define glr2 r12 /* prologs, epilogs, glink routines, calls by * pointer(EABI), language specific purpouse (SVR4), * glue code, exception handling (PO), volatile */ #define retval0 r3 /* return register 0, volatile */ #define retval1 r4 /* return register 1, volatile */ /* non-volatile and dedicated registers saved across subroutine calls */ #define sp r1 /* stack pointer, dedicated */ #define t0 r14 /* temporary registers, non-volatile */ #define t1 r15 /* temporary registers, non-volatile */ #define t2 r16 /* temporary registers, non-volatile */ #define t3 r17 /* temporary registers, non-volatile */ #define t4 r18 /* temporary registers, non-volatile */ #define t5 r19 /* temporary registers, non-volatile */ #define t6 r20 /* temporary registers, non-volatile */ #define t7 r21 /* temporary registers, non-volatile */ #define t8 r22 /* temporary registers, non-volatile */ #define t9 r23 /* temporary registers, non-volatile */ #define t10 r24 /* temporary registers, non-volatile */ #define t11 r25 /* temporary registers, non-volatile */ #define t12 r26 /* temporary registers, non-volatile */ #define t13 r27 /* temporary registers, non-volatile */ #define t14 r28 /* temporary registers, non-volatile */ #define t15 r29 /* temporary registers, non-volatile */ #define t16 r30 /* temporary registers, non-volatile */ #define t17 r31 /* temporary registers, non-volatile */ /* GP register names */ #define r0 0 #define r1 1 #define r2 2 #define r3 3 #define r4 4 #define r5 5 #define r6 6 #define r7 7 #define r8 8 #define r9 9 #define r10 10 #define r11 11 #define r12 12 #define r13 13 #define r14 14 #define r15 15 #define r16 16 #define r17 17 #define r18 18 #define r19 19 #define r20 20 #define r21 21 #define r22 22 #define r23 23 #define r24 24 #define r25 25 #define r26 26 #define r27 27 #define r28 28 #define r29 29 #define r30 30 #define r31 31 /* FP register names */ #define fp0 0 #define fr0 0 #define f0 0 #define fp1 1 #define fr1 1 #define f1 1 #define fp2 2 #define fr2 2 #define f2 2 #define fp3 3 #define fr3 3 #define f3 3 #define fp4 4 #define fr4 4 #define f4 4 #define fp5 5 #define fr5 5 #define f5 5 #define fp6 6 #define fr6 6 #define f6 6 #define fp7 7 #define fr7 7 #define f7 7 #define fp8 8 #define fr8 8 #define f8 8 #define fp9 9 #define fr9 9 #define f9 9 #define fp10 10 #define fr10 10 #define f10 10 #define fp11 11 #define fr11 11 #define f11 11 #define fp12 12 #define fr12 12 #define f12 12 #define fp13 13 #define fr13 13 #define f13 13 #define fp14 14 #define fr14 14 #define f14 14 #define fp15 15 #define fr15 15 #define f15 15 #define fp16 16 #define fr16 16 #define f16 16 #define fp17 17 #define fr17 17 #define f17 17 #define fp18 18 #define fr18 18 #define f18 18 #define fp19 19 #define fr19 19 #define f19 19 #define fp20 20 #define fr20 20 #define f20 20 #define fp21 21 #define fr21 21 #define f21 21 #define fp22 22 #define fr22 22 #define f22 22 #define fp23 23 #define fr23 23 #define f23 23 #define fp24 24 #define fr24 24 #define f24 24 #define fp25 25 #define fr25 25 #define f25 25 #define fp26 26 #define fr26 26 #define f26 26 #define fp27 27 #define fr27 27 #define f27 27 #define fp28 28 #define fr28 28 #define f28 28 #define fp29 29 #define fr29 29 #define f29 29 #define fp30 30 #define fr30 30 #define f30 30 #define fp31 31 #define fr31 31 #define f31 31 /* Condition register names */ #define cr0 0 #define cr1 1 #define cr2 2 #define cr3 3 #define cr4 4 #define cr5 5 #define cr6 6 #define cr7 7 /* Macro for hiadjust and lo */ #define HIADJ(arg) arg@ha #define HI(arg) arg@h #define LO(arg) arg@l #ifdef _PPC_MSR_VEC /* ALTIVEC Vector register names */ #define v0 0 #define v1 1 #define v2 2 #define v3 3 #define v4 4 #define v5 5 #define v6 6 #define v7 7 #define v8 8 #define v9 9 #define v10 10 #define v11 11 #define v12 12 #define v13 13 #define v14 14 #define v15 15 #define v16 16 #define v17 17 #define v18 18 #define v19 19 #define v20 20 #define v21 21 #define v22 22 #define v23 23 #define v24 24 #define v25 25 #define v26 26 #define v27 27 #define v28 28 #define v29 29 #define v30 30 #define v31 31 #endif /* special purpose register encoding */ #define XER 1 /* external exception register */ #define LR 8 /* link register (return address) */ #define CTR 9 /* counter register */ #define DSISR 18 /* data storage interrupt status */ #define DAR 19 /* data address register */ #define DEC 22 /* decrement register */ #define SDR1 25 /* storage description register 1 */ #define SRR0 26 /* save and restore register 0 */ #define SRR1 27 /* save and restore register 1 */ #define SPRG0 272 /* software program register 0 */ #define SPRG1 273 /* software program register 1 */ #define SPRG2 274 /* software program register 2 */ #define SPRG3 275 /* software program register 3 */ #define SPRG4 276 /* software program register 4 */ #define SPRG5 277 /* software program register 5 */ #define SPRG6 278 /* software program register 6 */ #define SPRG7 279 /* software program register 7 */ #define ASR 280 /* address space register * (64 bit implementation only) */ #define EAR 282 /* external address register */ #define TBL 284 /* lower time base register */ #define TBU 285 /* upper time base register */ #define PVR 287 /* processor version register */ #define IBAT0U 528 /* instruction BAT register */ #define IBAT0L 529 /* instruction BAT register */ #define IBAT1U 530 /* instruction BAT register */ #define IBAT1L 531 /* instruction BAT register */ #define IBAT2U 532 /* instruction BAT register */ #define IBAT2L 533 /* instruction BAT register */ #define IBAT3U 534 /* instruction BAT register */ #define IBAT3L 535 /* instruction BAT register */ #define DBAT0U 536 /* data BAT register */ #define DBAT0L 537 /* data BAT register */ #define DBAT1U 538 /* data BAT register */ #define DBAT1L 539 /* data BAT register */ #define DBAT2U 540 /* data BAT register */ #define DBAT2L 541 /* data BAT register */ #define DBAT3U 542 /* data BAT register */ #define DBAT3L 543 /* data BAT register */ #define IBAT4U 560 /* instruction BAT register */ #define IBAT4L 561 /* instruction BAT register */ #define IBAT5U 562 /* instruction BAT register */ #define IBAT5L 563 /* instruction BAT register */ #define IBAT6U 564 /* instruction BAT register */ #define IBAT6L 565 /* instruction BAT register */ #define IBAT7U 566 /* instruction BAT register */ #define IBAT7L 567 /* instruction BAT register */ #define DBAT4U 568 /* data BAT register */ #define DBAT4L 569 /* data BAT register */ #define DBAT5U 570 /* data BAT register */ #define DBAT5L 571 /* data BAT register */ #define DBAT6U 572 /* data BAT register */ #define DBAT6L 573 /* data BAT register */ #define DBAT7U 574 /* data BAT register */ #define DBAT7L 575 /* data BAT register */ #define BO_dCTR_NZERO_AND_NOT 0 #define BO_dCTR_ZERO_AND_NOT 2 #define BO_IF_NOT 4 #define BO_dCTR_ZERO_AND 10 #define BO_IF 12 #define BO_dCTR_NZERO 16 #define BO_dCTR_ZERO 18 #define BO_ALWAYS 20 #define CR0_LT 8 /* macros to mask one bit off using rotate left word immediate then and * with mask instruction by setting SH to zero, MB to n+1, ME to n-1. */ #ifndef INT_MASK #define INT_MASK(src, des) rlwinm des, src, 0, 17, 15 #endif /* INT_MASK */ #define RI_MASK(src, des) rlwinm des, src, 0, 31, 29 #define SE_MASK(src, des) rlwinm des, src, 0, 22, 20 #define IC_MASK(src, des) rlwinm des, src, 0, 5, 3 #define FRAMEBASESZ 16 /* Special Purpose Register PowerPC604 specific */ #define IMMR 638 /* Internal mem map reg - from 82xx slave SIU */ #undef ASR /* 64 bit implementation only */ #define MMCR0 952 /* Monitor Mode Control Register 0 */ #define PMC1 953 /* Performance Monitor Counter Register 1 */ #define PMC2 954 /* Performance Monitor Counter Register 2 */ #define SIA 955 /* Sampled Instruction Address Register */ #define SDA 959 /* Sampled Data Address Register */ #define HID0 1008 /* hardware implementation register 0 */ #define HID1 1009 /* hardware implementation register 1 */ #define HID2 1011 /* hardware implementation register 2 (MPC755)*/ #define IABR 1010 /* Instruction Address Breakpoint Register */ #define DABR 1013 /* Data Address Breakpoint Register */ #define PIR 1023 /* Processor Identification Register */ #ifdef _CACHE_ALIGN_SIZE #undef _CACHE_ALIGN_SIZE #endif /* _CACHE_ALIGN_SIZE */ #define _CACHE_ALIGN_SIZE 32 /* cache line size */ /* spr976 - DMISS data tlb miss address register * spr977 - DCMP data tlb miss compare register * spr978 - HASH1 PTEG1 address register * spr980 - HASH2 PTEG2 address register * IMISS - instruction tlb miss address register * ICMP - instruction TLB mis compare register * RPA - real page address register * HID0 - hardware implemntation register * HID2 - instruction address breakpoint register */ #define _PPC_HID0_EMCP 0x80000000 /* Enable machine check pin */ #define _PPC_HID0_ECPC 0x40000000 /* Enable cache parity check */ #define _PPC_HID0_EBA 0x20000000 /* Enable address bus parity */ #define _PPC_HID0_EBD 0x10000000 /* Enable data bus parity */ #define _PPC_HID0_PAR 0x01000000 #define _PPC_HID0_NHR 0x00010000 /* Not hard reset */ #define _PPC_HID0_ICE 0x00008000 /* inst cache enable */ #define _PPC_HID0_DCE 0x00004000 /* data cache enable */ #define _PPC_HID0_ILOCK 0x00002000 /* inst cache lock */ #define _PPC_HID0_DLOCK 0x00001000 /* data cache lock */ #define _PPC_HID0_ICFI 0x00000800 /* inst cache flash invalidate*/ #define _PPC_HID0_DCFI 0x00000400 /* data cache flash invalidate*/ #define _PPC_HID0_SIED 0x00000080 /* serial instr exec disable */ #define _PPC_HID0_BHTE 0x00000004 /* branch history table enable*/ #define _PPC_HID0_XBSEN 0x0100 /* Extended Block Size enable */ #define _PPC_HID0_HIGH_BAT_EN_U 0x0080 /* High Bat enable on MPC7455 */ #define _PPC_HID2_HIGH_BAT_EN_U 0x0004 /* High Bat enable on MPC755 */ #define PVR 287 /* processor version register */ /* HID0 bit definitions */ #define _PPC_HID0_BIT_ICE 16 /* HID0 ICE bit for 604 */ #define _PPC_HID0_BIT_DCE 17 /* HID0 DCE bit for 604 */ #define _PPC_HID0_BIT_ILOCK 18 /* HID0 ILOCK bit for 604 */ #define _PPC_HID0_BIT_DLOCK 19 /* HID0 DLOCK bit for 604 */ #define _PPC_HID0_BIT_ICFI 20 /* HID0 ICFI bit for 604 */ #define _PPC_HID0_BIT_DCFI 21 /* HID0 DCFI bit for 604 */ #define _PPC_HID0_BIT_SIED 24 /* HID0 SIED bit for 604 */ #define _PPC_HID0_BIT_BHTE 29 /* HID0 BHTE bit for 604 */ #define _PPC_HID0_BIT_XBSEN 23 /* HID0 XBSEN bit for 7455 */ #define _PPC_HID0_BIT_HIGH_BAT_EN 8 /* HID0 HIGH_BAT_EN bit for 7455 */ #define _PPC_HID2_BIT_HIGH_BAT_EN 13 /* HID0 HIGH_BAT_EN bit for 755 */ /* MSR bit definitions */ #define _PPC_MSR_BIT_POW 13 /* MSR Power Management bit - POW */ #define _PPC_MSR_BIT_ILE 15 /* MSR Excep little endian bit - ILE */ #define _PPC_MSR_BIT_FP 18 /* MSR Floating Ponit Aval. bit - FP */ #define _PPC_MSR_BIT_FE0 20 /* MSR FP exception mode 0 bit - FE0 */ #define _PPC_MSR_BIT_SE 21 /* MSR Single Step Trace bit - SE */ #define _PPC_MSR_BIT_BE 22 /* MSR Branch Trace Enable bit - BE */ #define _PPC_MSR_BIT_FE1 23 /* MSR FP exception mode 1 bit - FE1 */ #define _PPC_MSR_BIT_IP 25 /* MSR Exception Prefix bit - EP */ #define _PPC_MSR_BIT_IR 26 /* MSR Inst Translation bit - IR */ #define _PPC_MSR_BIT_DR 27 /* MSR Data Translation bit - DR */ #define _PPC_MSR_BIT_PM 29 /* MSR Performance Monitor bit - MR */ #define _PPC_MSR_BIT_RI 30 /* MSR Exception Recoverable bit - RI */ #ifdef _WRS_ALTIVEC_SUPPORT #define _PPC_MSR_VEC 0x0200 /* Bit 6 of MSR */ #define _PPC_MSR_BIT_VEC 06 /* MSR Altivec Available bit - VEC */ #endif /* PPC604 specific exceptions */ /* * the PERF excExtConnectCode stub (extended vector) won't fit at the * default location 0xf00 because _EXC_ALTIVEC_UNAVAILABLE is at 0x0f20, * so we need to put them where we've got some available space and jump * to it from _EXC_OFF_PERF. The stub being 22 long words max currently * (including 4xx critical exception and extended vectors), 0x0f80 - 0x0f20 * = 0x60 = 96 >= 88 = 22 * 4 has enough room for _EXC_ALTIVEC_UNAVAILABLE. */ #define _EXC_OFF_PERF 0x0f00 /* performance monitoring intr*/ #define _EXC_NEW_OFF_PERF 0x0f80 /* relocated perf monitor */ #define _EXC_OFF_INST_BKPT 0x1300 /* instruction address BP */ #define _EXC_OFF_THERMAL 0x1700 /* performance monitoring intr*/ /* IABR bit definitions */ /* set and get address in IABR */ #define _PPC_IABR_ADD(x) ((x) & 0xFFFFFFFC) #define _PPC_IABR_BE 0x00000002 /* breakpoint enabled */ #define _PPC_IABR_TE 0x00000001 /* translation enabled */ /* DABR bits definition */ /* set and get address in DABR */ #define _PPC_DABR_DAB(x) ((x) & 0xFFFFFFF8) #define _PPC_DABR_BT 0x00000004 /* breakpoint translation */ #define _PPC_DABR_DW 0x00000002 /* data write enable */ #define _PPC_DABR_DR 0x00000001 /* data read enable */ /* mask for read and write operations */ #define _PPC_DABR_D_MSK (_PPC_DABR_DW | _PPC_DABR_DR) /* DSISR bits definition */ #define _PPC_DSISR_BRK 0x00400000 /* DABR match occurs */ #endif