www.pudn.com > vxworks0108.rar > ppc750.h
/*
This file contains addresses and constants specific for MPC 750
*/
#ifndef INC_ppc750_h
#define INC_ppc750_h
#include "ppc604.h"
#ifdef __cplusplus
extern "C" {
#endif
/* BAT stuff */
#define BATU(vadr, size) (((vadr))|(size))
#define BATL(radr, wimg) (((radr))|(wimg)|0x2)
#define BAT_512M 0x3ffe
#define BAT_256M 0x1ffe
#define BAT_128M 0x0ffe
#define BAT_64M 0x07fe
#define BAT_32M 0x03fe
#define BAT_16M 0x01fe
#define BAT_8M 0x00fe
#define BAT_4M 0x007e
#define BAT_W 0x40
#define BAT_I 0x20
#define BAT_M 0x10
#define BAT_G 0x08
#define CACHELINESIZE 32 /* For now XXX */
#ifndef _ASMLANGUAGE
struct bat {
UINT32 batu;
UINT32 batl;
};
void savebat(struct bat *);
void loadbat(struct bat *);
extern struct bat trapbat;
#endif
#define L2CR_REG 1017 /* l2CR register number */
#define HID0_REG 1008
#define PVR_REG 287 /* pvr register number */
#define ARTHUR 8 /* Upper bit 16 bit value of 740/750 */
#define WRITE_ADDR_U 0x0060 /* upper 16 bits of write address */
#define L2_SIZE_1M_U 0x0010 /* upper 16 bitts of 1 Meg */
#define L2_ADR_INCR 0x100 /* address increament value */
#define L2_SIZE_1M 0x1000 /* 1 MG (0x100000) / 0x100 = 0x1000 */
#define L2_SIZE_HM 0x800 /* 512K counts */
#define L2_SIZE_QM 0x400 /* 256K(0x40000) / L2_ADR_INCR = 0x40 */
/*
* Defining values for L2CR register:
* - L2 cache enable (1) / disable (0) (bit 0)
* - cache size (bits 2-3; 3: 1 MB, 2: 512 KB, 1: 256 KB)
* - 1.5 clock ratio (bits 4-6)
* - Pinpelined (register-register) synchronous burst RAM (bits 7-8)
* - L2 Data only (bit 9)
* - Test mode on (1) or off (0) (bit 13)
*
*/
/* L2 Data Parity generation and checking enable */
#define L2CR_PE 0x4000
/* values for the L2SIZ bits */
#define L2CR_SIZE_2MB 0x0000
#define L2CR_SIZE_256KB 0x1000
#define L2CR_SIZE_512KB 0x2000
#define L2CR_SIZE_1MB 0x3000
/* values for L2CLK bits */
#define L2CR_CLK_DISABLE 0x0000
#define L2CR_CLK_1 0x0200
#define L2CR_CLK_1_5 0x0400
#define L2CR_CLK_3_5 0x0600
#define L2CR_CLK_2 0x0800
#define L2CR_CLK_2_5 0x0a00
#define L2CR_CLK_3 0x0c00
#define L2CR_CLK_4 0x0e00
/* values for L2RAM Type */
#define L2CR_RAM_SYNBRST 0x0000 /* synchronous burst SRAM */
#define L2CR_RAM_PB3 0x0080 /* PB3 synchronous burst SRAM (7xx)*/
#define L2CR_RAM_PB2 0x0100 /* PB2 synchronous burst SRAM */
#define L2CR_RAM_SYNLTWRT 0x0180 /* Synchronouus Late write SRAM */
/* L2 data only */
#define L2DO 0x0040
/* L2 Global invalidate */
#define L2CR_GBL_INV_U 0x0020
/* L2 Ram Control (ZZ enable) */
#define L2CR_RAMCTL 0x0010
/* L2 Write Through */
#define L2CR_WT 0x0008
/* L2 Test Support */
#define L2CR_TS 0x0004
/* L2 Output Hold */
#define L2CR_OH_0_5ns 0x0000
#define L2CR_OH_1_0ns 0x0001
#define L2CR_OH_MORE 0x0002
#define L2CR_OH_EVEN_MORE 0x0003
/* L2 Ins. only mode */
#define L2IO 0x0400
#define L2CR_CFG ( L2_CACHE_SIZE | \
L2CR_RAM_PB2 | \
L2CR_WT | \
L2CR_OH_0_5ns)
#define L2CR_DISABLE_MASK_U 0x7fff /* Disable L2 - upper 16 bits */
#define L2CR_EN_U 0x8000 /* Set L2CR enable bit */
#define L2CR_FA 0x1000 /* flush assist (software flush) */
#define L2CR_HWF 0x0800 /* hardware flush */
#define L2CR_IP 0x0001 /* Invalidation in progress */
#ifdef INCLUDE_L2PM
/* L2PM Register address */
#define L2PM_REG 1016
/* Base Address for the L2 Private Memory equivalent to mem size*/
#define L2PMBA ( L2PM_SRAM_ADRS >> 16 )
/* L2PM_SIz bit configration to determine the size of L2 private memeory */
#define L2PM_SIZE_256KB 0x0001
#define L2PM_SIZE_512KB 0x0002
#define L2PM_SIZE_1M 0x0003
#endif
#define L1_DCACHE_ENABLE 0x4400
#define L1_DCACHE_INV_MASK 0xfbff
#define L1_DCACHE_DISABLE 0xbfff
/* special purpose register encoding */
#define XER 1 /* external exception register */
#define LR 8 /* link register (return address) */
#define CTR 9 /* counter register */
#define DSISR 18 /* data storage interrupt status */
#define DAR 19 /* data address register */
#define DEC 22 /* decrement register */
#define SDR1 25 /* storage description register 1 */
#define SRR0 26 /* save and restore register 0 */
#define SRR1 27 /* save and restore register 1 */
#define SPRG0 272 /* software program register 0 */
#define SPRG1 273 /* software program register 1 */
#define SPRG2 274 /* software program register 2 */
#define SPRG3 275 /* software program register 3 */
#define SPRG4 276 /* software program register 4 */
#define SPRG5 277 /* software program register 5 */
#define SPRG6 278 /* software program register 6 */
#define SPRG7 279 /* software program register 7 */
#define ASR 280 /* address space register
* (64 bit implementation only) */
#define EAR 282 /* external address register */
#define TBL 284 /* lower time base register */
#define TBU 285 /* upper time base register */
#define PVR 287 /* processor version register */
#define IBAT0U 528 /* instruction BAT register */
#define IBAT0L 529 /* instruction BAT register */
#define IBAT1U 530 /* instruction BAT register */
#define IBAT1L 531 /* instruction BAT register */
#define IBAT2U 532 /* instruction BAT register */
#define IBAT2L 533 /* instruction BAT register */
#define IBAT3U 534 /* instruction BAT register */
#define IBAT3L 535 /* instruction BAT register */
#define DBAT0U 536 /* data BAT register */
#define DBAT0L 537 /* data BAT register */
#define DBAT1U 538 /* data BAT register */
#define DBAT1L 539 /* data BAT register */
#define DBAT2U 540 /* data BAT register */
#define DBAT2L 541 /* data BAT register */
#define DBAT3U 542 /* data BAT register */
#define DBAT3L 543 /* data BAT register */
#define IBAT4U 560 /* instruction BAT register */
#define IBAT4L 561 /* instruction BAT register */
#define IBAT5U 562 /* instruction BAT register */
#define IBAT5L 563 /* instruction BAT register */
#define IBAT6U 564 /* instruction BAT register */
#define IBAT6L 565 /* instruction BAT register */
#define IBAT7U 566 /* instruction BAT register */
#define IBAT7L 567 /* instruction BAT register */
#define DBAT4U 568 /* data BAT register */
#define DBAT4L 569 /* data BAT register */
#define DBAT5U 570 /* data BAT register */
#define DBAT5L 571 /* data BAT register */
#define DBAT6U 572 /* data BAT register */
#define DBAT6L 573 /* data BAT register */
#define DBAT7U 574 /* data BAT register */
#define DBAT7L 575 /* data BAT register */
#define BO_dCTR_NZERO_AND_NOT 0
#define BO_dCTR_ZERO_AND_NOT 2
#define BO_IF_NOT 4
#define BO_dCTR_ZERO_AND 10
#define BO_IF 12
#define BO_dCTR_NZERO 16
#define BO_dCTR_ZERO 18
#define BO_ALWAYS 20
#define CR0_LT 8
/* macros to mask one bit off using rotate left word immediate then and
* with mask instruction by setting SH to zero, MB to n+1, ME to n-1. */
#ifndef INT_MASK
#define INT_MASK(src, des) rlwinm des, src, 0, 17, 15
#endif /* INT_MASK */
#define RI_MASK(src, des) rlwinm des, src, 0, 31, 29
#define SE_MASK(src, des) rlwinm des, src, 0, 22, 20
#define IC_MASK(src, des) rlwinm des, src, 0, 5, 3
/* L2CR cache control register (MPC750 - Arthur) */
#define MPC750_L2CR_E 0x80000000
#define MPC750_L2CR_256K 0x10000000
#define MPC750_L2CR_512K 0x20000000
#define MPC750_L2CR_1024K 0x30000000
#define MPC750_L2CR_CLK_DIS 0x00000000 /* disable clock and dll */
#define MPC750_L2CR_CLK_10 0x02000000 /* core to L2 divider: 1.0 ns */
#define MPC750_L2CR_CLK_15 0x04000000 /* core to L2 divider: 1.5 ns */
#define MPC750_L2CR_CLK_20 0x08000000 /* core to L2 divider: 2.0 ns */
#define MPC750_L2CR_CLK_25 0x0a000000 /* core to L2 divider: 2.5 ns */
#define MPC750_L2CR_CLK_30 0x0c000000 /* core to L2 divider: 3.0 ns */
#define MPC750_L2CR_FBSRAM 0x00000000 /* flow-through synchronous burst RAM */
#define MPC750_L2CR_PBSRAM 0x01000000 /* pipelined synchronous burst RAM */
#define MPC750_L2CR_PLSRAM 0x01800000 /* pipelined synchronous late-write RAM */
#define MPC750_L2CR_DO 0x00400000 /* L2 data only */
#define MPC750_L2CR_I 0x00200000
#define MPC750_L2CR_CTL 0x00100000
#define MPC750_L2CR_OH_05 0x00000000
#define MPC750_L2CR_OH_10 0x00010000
#define MPC750_L2CR_SL 0x00008000
#define MPC750_L2CR_FA 0x00001000 /* 7400 software flash assist bit */
#define MPC750_L2CR_HWF 0x00000800 /* 7400 hardware flash bit */
#define MPC750_L2CR_IP 0x00000001
#define MPC750_L2CR_SIZE_MSK 0x30000000
#define MPC750_L2CR_CLK_MSK 0x0e000000
/* Thermal Management register (MPC750 - Arthur) */
#define MPC750_THRM_TIN 0x80000000
#define MPC750_THRM_TIV 0x40000000
#define MPC750_THRM_TID 0x00000004
#define MPC750_THRM_TIE 0x00000002
#define MPC750_THRM_V 0x00000001
#define MPC750_THRM3_E 0x00000001
#ifndef _PPC_HID0_SGE
# define _PPC_HID0_SGE 0x00000080 /* branch instruction cache enable */
#endif
#ifndef _PPC_HID0_BTIC
# define _PPC_HID0_BTIC 0x00000020 /* branch instruction cache disable */
#endif
#ifndef _PPC_HID0_ABE
# define _PPC_HID0_ABE 0x00000008 /* address broadcast enable */
#endif
/* L2 Cache Control Register */
#ifndef L2CR
# define L2CR 1017
#endif
/* Thermal Management Register 1 */
#ifndef THRM1
# define THRM1 1020
#endif
/* Thermal Management Register 2 */
#ifndef THRM2
# define THRM2 1021
#endif
/* Thermal Management Register 3 */
#ifndef THRM3
# define THRM3 1022
#endif
/*
* Bit settings for PLL configuration in HID1 register
*/
#define PPC750_PLL_CFG_7_5 0x1
#define PPC750_PLL_CFG_7 0x2
#define PPC750_PLL_CFG_2 0x4
#define PPC750_PLL_CFG_6_5 0x5
#define PPC750_PLL_CFG_10 0x6
#define PPC750_PLL_CFG_4_5 0x7
#define PPC750_PLL_CFG_3 0x8
#define PPC750_PLL_CFG_5_5 0x9
#define PPC750_PLL_CFG_4 0xA
#define PPC750_PLL_CFG_5 0xB
#define PPC750_PLL_CFG_8 0xC
#define PPC750_PLL_CFG_6 0xD
#define PPC750_PLL_CFG_3_5 0xE
/*
* Additional special purpose registers SPRG[4-7] for 755 processors.
*/
#ifndef SPRG4
# define SPRG4 276
#endif
#ifndef SPRG5
# define SPRG5 277
#endif
#ifndef SPRG6
# define SPRG6 278
#endif
#ifndef SPRG7
# define SPRG7 279
#endif
/*
* Additional block address translation entries (IBAT[4-7] and DBAT[4-7])
* for 755 processors.
*/
#ifndef IBAT4U
# define IBAT4U 560
#endif
#ifndef IBAT4L
# define IBAT4L 561
#endif
#ifndef IBAT5U
# define IBAT5U 562
#endif
#ifndef IBAT5L
# define IBAT5L 563
#endif
#ifndef IBAT6U
# define IBAT6U 564
#endif
#ifndef IBAT6L
# define IBAT6L 565
#endif
#ifndef IBAT7U
# define IBAT7U 566
#endif
#ifndef IBAT7L
# define IBAT7L 567
#endif
#ifndef DBAT4U
# define DBAT4U 568
#endif
#ifndef DBAT4L
# define DBAT4L 569
#endif
#ifndef DBAT5U
# define DBAT5U 570
#endif
#ifndef DBAT5L
# define DBAT5L 571
#endif
#ifndef DBAT6U
# define DBAT6U 572
#endif
#ifndef DBAT6L
# define DBAT6L 573
#endif
#ifndef DBAT7U
# define DBAT7U 574
#endif
#ifndef DBAT7L
# define DBAT7L 575
#endif
/*
* Additional special purpose registers SPRG[4-7] for 755 processors.
*/
#ifndef HID2
# define HID2 1011
#endif
/*
* Additional L2 private memory control register L2PM for 755 processors.
*/
#ifndef L2PM
# define L2PM 1016
#endif
#if 0
#define INSTRUCTION_CACHE 0 /* Instruction Cache(s) */
#define DATA_CACHE 1 /* Data Cache(s) */
#endif
#ifdef __cplusplus
}
#endif
#endif /* INC_ppc750_h */