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/* mpc107.h - MPC107 EPIC definitions */
/*
Description:
Contains structure typedefs and device-specific defines for the Motorola EPIC (MPC107)
*/
#ifndef INC_mpc107_h
#define INC_mpc107_h
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
/* MPC107 device and vendor ID's */
#define MPC107_DEV_VEN_ID 0x1057 /* vendor for Motorola */
/* MPC107 configuration adrs and data register for map A & B */
#define MPC107_CFG_ADDR_PREP 0x80000cf8 /* MPC107 cfg reg map A */
#define MPC107_CFG_DATA_PREP 0x80000cfc /* MPC107 cfg data map A */
#define MPC107_CFG_ADDR_CHRP 0xfec00000 /* MPC107 cfg reg map B */
#define MPC107_CFG_DATA_CHRP 0xfee00000 /* MPC107 cfg data map B */
#define MPC107_PICR1_MAPB 0x0 /* PICR1 bit 16 map B */
#define MPC107_PICR1_MAPA 0x1 /* PICR1 bit 16 map A */
#define MPC107_MCCR1_ADRS (MPC107_CFG_BASE + 0xf0) /* MCCR1 */
#define MPC107_MCCR2_ADRS (MPC107_CFG_BASE + 0xf4) /* MCCR2 */
#define MPC107_MCCR3_ADRS (MPC107_CFG_BASE + 0xf8) /* MCCR3 */
#define MPC107_MCCR4_ADRS (MPC107_CFG_BASE + 0xfc) /* MCCR4 */
#define MPC107_MBER_ADRS (MPC107_CFG_BASE + 0xa0) /* MBER */
/* addresses */
/* MPC107 indirect configuration registers */
#define MPC107_CFG_BASE 0x80000000 /* Base adrs of cfg regs */
#define MPC107_CFG_BASE_16 0x8000 /* MPC107_CFG_BASE >> 16 */
#define CHAPARRAL_REG MPC107_CFG_BASE_16
/* MPC107 Registers */
#define MPC107_VEND_ID 0x0000
#define MPC107_DEV_ID 0x0002
#define MPC107_PCI_CMD 0x0004
#define MPC107_PCI_STAT 0x0006
#define MPC107_DEV_REV 0x0008
#define MPC107_SPI 0x0009
#define MPC107_PCISBCC 0x000A
#define MPC107_PCIBCC 0x000B
#define MPC107_PCICLS 0x000C
#define MPC107_LMBBAR 0x0010
#define MPC107_PCSRBAR 0x0014
#define MPC107_PCIACR 0x0046
#define MPC107_PFMCMD 0x0048
#define MPC107_PFMMCR 0x004C
#define MPC107_PFMCNT0 0x0050
#define MPC107_PFMCNT1 0x0054
#define MPC107_PFMCNT2 0x0058
#define MPC107_PFMCNT3 0x005C
#define MPC107_PMCR1 0x0070
#define MPC107_PMCR2 0x0072
#define MPC107_ODCR 0x0073
#define MPC107_CDCR 0x0074
#define MPC107_MDCR 0x0076
#define MPC107_EUMBBAR 0x0078
#define MPC107_MSAR1 0x0080
#define MPC107_MSAR2 0x0084
#define MPC107_EMSAR1 0x0088
#define MPC107_EMSAR2 0x008c
#define MPC107_MEAR1 0x0090
#define MPC107_MEAR2 0x0094
#define MPC107_EMEAR1 0x0098
#define MPC107_EMEAR2 0x009c
#define MPC107_MBEN 0x00a0
#define MPC107_MPMR 0x00a3
#define MPC107_PRC1 0x00a8
#define MPC107_PRC2 0x00ac
#define MPC107_ECCSBEC 0x00b8
#define MPC107_ECCSBETR 0x00b9
#define MPC107_EER1 0x00c0
#define MPC107_EDR1 0x00c1
#define MPC107_CBESR 0x00c3
#define MPC107_EER2 0x00c4
#define MPC107_EDR2 0x00c5
#define MPC107_PBESR 0x00c7
#define MPC107_CPEAR 0x00c8
#define MPC107_AMBOR 0x00e0
#define MPC107_MCCR1 0x00f0
#define MPC107_MCCR2 0x00f4
#define MPC107_MCCR3 0x00f8
#define MPC107_MCCR4 0x00fc
/*
* Chaparral (MPC107) register bit masks
*
* Bits marked with 'C' indicate conditions which can be cleared by
* writing a 1 to the bits.
*/
/* Processor Interface Config. Reg 1 */
#define MPC107_PRC1_MCP_EN 0x00000800 /* Machine check enable */
/* Chaparral PCI Configuration Status register bit masks */
#define MPC107_PCI_STAT_FAST 0x0080 /* Fast back-to-back capable */
#define MPC107_PCI_STAT_DPAR 0x0100 /* C Data parity error detected */
#define MPC107_PCI_STAT_SELTIM0 0x0200 /* Device select timing bit 0 */
#define MPC107_PCI_STAT_SELTIM1 0x0400 /* Device select timing bit 1 */
#define MPC107_PCI_STAT_SIGTA 0x0800 /* C Signaled Target Abort */
#define MPC107_PCI_STAT_RCVTA 0x1000 /* C Received Target Abort */
#define MPC107_PCI_STAT_RCVMA 0x2000 /* C Received Master Abort */
#define MPC107_PCI_STAT_SIGSE 0x4000 /* C Signaled System Error */
#define MPC107_PCI_STAT_RCVPE 0x8000 /* C Detected Parity Error */
#define MPC107_PCI_STAT_VALID 0xFF80 /* Valid status bits */
#define MPC107_PCI_STAT_CLR 0xF900 /* Clears all conditions */
/* Chaparral Memory Control Configuration Register 2 (MCCR2) bit masks */
#define MPC107_MCCR2_INLPARNOTECC (1 << 20) /* In-line parity - not ECC */
/* Chaparral Error Enabling Register 1 bit masks */
#define MPC107_EER1_PTEE 0x01 /* Processor Transaction Error Enable */
#define MPC107_EER1_PCIMAEE 0x02 /* PCI Master-Abort Error Enable */
#define MPC107_EER1_MPECCEE 0x04 /* Memory Parity/single-bit ECC Enable */
#define MPC107_EER1_PCIMPERRE 0x08 /* PCI Master PERR Enable */
#define MPC107_EER1_MROEE 0x10 /* Memory Refresh Overflow Enable */
#define MPC107_EER1_MSEE 0x20 /* Memory Select Error Enable */
#define MPC107_EER1_PCITPERRE 0x40 /* PCI Target PERR Enable */
#define MPC107_EER1_RXSERREN 0x80 /* RX_SERR_EN */
/* Chaparral Error Enabling Register 2 bit masks */
#define MPC107_EER2_FROMWEE 0x01 /* Flash ROM Write Error Enable */
#define MPC107_EER2_PCIRTAEE 0x02 /* PCI Received Target Abort Error Enable */
#define MPC107_EER2_PMWPEE 0x04 /* Processor/Memory Write Parity Error Enable */
#define MPC107_EER2_ECCMEE 0x08 /* ECC Multibit Error Enable */
#define MPC107_EER2_PCISERREE 0x40 /* PCI SERR Enable */
#define MPC107_EER2_PCIAPEE 0x80 /* PCI Address Parity Error Enable */
/* Chaparral Error Detection Register 1 bit masks */
#define MPC107_EDR1_SERR 0x80 /* PCI System Error */
#define MPC107_EDR1_PERR 0x40 /* PCI Parity Error */
#define MPC107_EDR1_MSE 0x20 /* Memory select error */
#define MPC107_EDR1_MRO 0x10 /* Memory refresh overflow error */
#define MPC107_EDR1_PPC 0x08 /* Processor/PCI cycle */
#define MPC107_EDR1_MRPE 0x04 /* Memory read parity error/ECC single-bit error trigger exceeded */
#define MPC107_EDR1_UPT 0x03 /* Unsupported processor transaction */
#define MPC107_EDR1_VALID 0xFF /* Mask for valid ErrDR1 bits */
#define MPC107_EDR1_CLR 0xFF /* Clears all errors */
/* Chaparral Error Detection Register 2 bit masks */
#define MPC107_EDR2_IEA 0x80 /* Invalid Error Address */
#define MPC107_EDR2_PSE 0x40 /* PCI SERR error */
#define MPC107_EDR2_EMBE 0x08 /* ECC multi-bit error */
#define MPC107_EDR2_PMWPE 0x04 /* Processor memory write parity error */
#define MPC107_EDR2_FRWE 0x01 /* Flash ROM write error */
#define MPC107_EDR2_VALID 0xCD /* Mask for valid ErrDR2 bits */
#define MPC107_EDR2_CLR 0xCD /* Clears all errors */
/*
* Epic address macro
*/
#define EPIC_ADDR(reg) (EPIC_BASE_ADRS + reg)
/*
* Chaparral EPIC bit masks and settings for the registers
*/
#define SET_MIXED_MODE 0x20000000
#define TIMER_INHIBIT 0x80000000
#define TIMER_TOGGLE_BIT 0x80000000
#define INT_MASK_BIT 0x80000000
#define RESET_CNTRLR 0x80000000
#define HIGH_POLARITY 0x00800000
#define LEVEL_SENSE 0x00400000
#define VECTOR_MASK 0x000000ff
#define DESTINATION_CPU0 0x00000001
#define PRIORITY_MASK 0x000f0000
#define PRIORITY_LVL0 0x00000000
#define PRIORITY_LVL1 0x00010000
#define PRIORITY_LVL2 0x00020000
#define PRIORITY_LVL3 0x00030000
#define PRIORITY_LVL4 0x00040000
#define PRIORITY_LVL5 0x00050000
#define PRIORITY_LVL6 0x00060000
#define PRIORITY_LVL7 0x00070000
#define PRIORITY_LVL8 0x00080000
#define PRIORITY_LVL9 0x00090000
#define PRIORITY_LVL10 0x000a0000
#define PRIORITY_LVL11 0x000b0000
#define PRIORITY_LVL12 0x000c0000
#define PRIORITY_LVL13 0x000d0000
#define PRIORITY_LVL14 0x000e0000
#define PRIORITY_LVL15 0x000f0000
/* I2C Address Register */
#define I2C_ADR_MSK 0x000000FE
#define I2C_ADR_SADR_SHF 0x00
/* I2C Frequency Divider Register */
#define I2C_FDR_MSK 0x00003F3F
#define I2C_FDR_DFFSR_SHF 0x08
#define I2C_FDR_DFFSR_MSK (0x0000003F << I2C_FDR_DFFSR_SHF)
#define I2C_FDR_DFFSR_VAL(x) (((x) << I2C_FDR_DFFSR_SHF) & I2C_FDR_DFFSR_MSK)
#define I2C_FDR_FDR_SHF 0x00
#define I2C_FDR_FDR_MSK (0x0000003F << I2C_FDR_FDR_SHF)
#define I2C_FDR_FDR_VAL(x) ((x) & I2C_FDR_FDR_MSK)
/* I2C Control Register */
#define I2C_CCR_SHF 0x00
#define I2C_CCR_MSK (0x000000FC << I2C_CCR_SHF)
#define I2C_CCR_VAL(x) ((x) & I2C_CCR_MSK)
#define I2C_CCR_RSTA 0x00000004
#define I2C_CCR_MTXAK 0x00000008
#define I2C_CCR_MTX 0x00000010
#define I2C_CCR_MSTA 0x00000020
#define I2C_CCR_MIEN 0x00000040
#define I2C_CCR_MEN 0x00000080
#define I2C_CCR_MDIS 0x00000000
#define I2C_CCR_MRX 0x00000000
/* I2C Data Register */
#define I2C_DR_MSK 0x000000FF
#define I2C_DR_VAL(x) ((x) & I2C_DR_MSK)
#define I2C_DR_RX 0x00000001
/* I2C Status Register */
#define I2C_SR_MSK 0x000000F7
#define I2C_SR_VAL(x) ((x) & I2C_SR_MSK)
#define I2C_SR_RXAK 0x00000001
#define I2C_SR_MIF 0x00000002
#define I2C_SR_SRW 0x00000004
#define I2C_SR_MAL 0x00000010
#define I2C_SR_MBB 0x00000020
#define I2C_SR_MAAS 0x00000040
#define I2C_SR_MCF 0x00000080
/* miscellaneous defines */
#define EPIC_REG_OFFSET 0x10
/*
* Chaparral EPIC register definitions
*/
/* feature reporting register */
#define EPIC_FEATURE_REG 0x01000
/* global configuration register */
#define EPIC_GLOBAL_CONFIG_REG 0x01020
/* interrupt configuration register */
#define EPIC_INT_CONFIG_REG 0x01030
/* vendor identification register */
#define EPIC_VENDOR_ID_REG 0x01080
/* processor init register */
#define EPIC_PROCESSOR_INIT_REG 0x01090
/* spurious vector register */
#define EPIC_SPUR_VEC_REG 0x010e0
/* timer frequency register */
#define EPIC_TIMER_FREQ_REG 0x010f0
/* number of timers available in EPIC */
#define EPIC_TIMER_CNT 4
/*
* timer registers 0-3
* - current count register
* - base count register
* - vector/priority register
* - destination register
*/
#define EPIC_TIMER0_CUR_CNT_REG 0x01100
#define EPIC_TIMER0_BASE_CT_REG 0x01110
#define EPIC_TIMER0_VEC_PRI_REG 0x01120
#define EPIC_TIMER0_DEST_REG 0x01130
#define EPIC_TIMER1_CUR_CNT_REG 0x01140
#define EPIC_TIMER1_BASE_CT_REG 0x01150
#define EPIC_TIMER1_VEC_PRI_REG 0x01160
#define EPIC_TIMER1_DEST_REG 0x01170
#define EPIC_TIMER2_CUR_CNT_REG 0x01180
#define EPIC_TIMER2_BASE_CT_REG 0x01190
#define EPIC_TIMER2_VEC_PRI_REG 0x011a0
#define EPIC_TIMER2_DEST_REG 0x011b0
#define EPIC_TIMER3_CUR_CNT_REG 0x011c0
#define EPIC_TIMER3_BASE_CT_REG 0x011d0
#define EPIC_TIMER3_VEC_PRI_REG 0x011e0
#define EPIC_TIMER3_DEST_REG 0x011f0
/*
* external source registers 0-4
* - vector/priority register
* - destination register
*/
#define EPIC_EXT_SRC0_VEC_PRI_REG 0x10200
#define EPIC_EXT_SRC0_DEST_REG 0x10210
#define EPIC_EXT_SRC1_VEC_PRI_REG 0x10220
#define EPIC_EXT_SRC1_DEST_REG 0x10230
#define EPIC_EXT_SRC2_VEC_PRI_REG 0x10240
#define EPIC_EXT_SRC2_DEST_REG 0x10250
#define EPIC_EXT_SRC3_VEC_PRI_REG 0x10260
#define EPIC_EXT_SRC3_DEST_REG 0x10270
#define EPIC_EXT_SRC4_VEC_PRI_REG 0x10280
#define EPIC_EXT_SRC4_DEST_REG 0x10290
/* number of external interrupt sources available in EPIC */
#define EPIC_EXT_SRC_CNT 5
/*
* SERIAL source registers 0-15
* - vector/priority register
* - destination register
*/
#define EPIC_SER_SRC0_VEC_PRI_REG 0x10200
#define EPIC_SER_SRC0_DEST_REG 0x10210
#define EPIC_SER_SRC1_VEC_PRI_REG 0x10220
#define EPIC_SER_SRC1_DEST_REG 0x10230
#define EPIC_SER_SRC2_VEC_PRI_REG 0x10240
#define EPIC_SER_SRC2_DEST_REG 0x10250
#define EPIC_SER_SRC3_VEC_PRI_REG 0x10260
#define EPIC_SER_SRC3_DEST_REG 0x10270
#define EPIC_SER_SRC4_VEC_PRI_REG 0x10280
#define EPIC_SER_SRC4_DEST_REG 0x10290
#define EPIC_SER_SRC5_VEC_PRI_REG 0x102a0
#define EPIC_SER_SRC5_DEST_REG 0x102b0
#define EPIC_SER_SRC6_VEC_PRI_REG 0x102c0
#define EPIC_SER_SRC6_DEST_REG 0x102d0
#define EPIC_SER_SRC7_VEC_PRI_REG 0x102e0
#define EPIC_SER_SRC7_DEST_REG 0x102f0
#define EPIC_SER_SRC8_VEC_PRI_REG 0x10300
#define EPIC_SER_SRC8_DEST_REG 0x10310
#define EPIC_SER_SRC9_VEC_PRI_REG 0x10320
#define EPIC_SER_SRC9_DEST_REG 0x10330
#define EPIC_SER_SRC10_VEC_PRI_REG 0x10340
#define EPIC_SER_SRC10_DEST_REG 0x10350
#define EPIC_SER_SRC11_VEC_PRI_REG 0x10360
#define EPIC_SER_SRC11_DEST_REG 0x10370
#define EPIC_SER_SRC12_VEC_PRI_REG 0x10380
#define EPIC_SER_SRC12_DEST_REG 0x10390
#define EPIC_SER_SRC13_VEC_PRI_REG 0x103a0
#define EPIC_SER_SRC13_DEST_REG 0x103b0
#define EPIC_SER_SRC14_VEC_PRI_REG 0x103c0
#define EPIC_SER_SRC14_DEST_REG 0x103d0
#define EPIC_SER_SRC15_VEC_PRI_REG 0x103e0
#define EPIC_SER_SRC15_DEST_REG 0x103f0
/* I2C interrupt registers */
#define EPIC_I2C_VEC_PRI_REG 0x11020
#define EPIC_I2C_DEST_REG 0x11030
/* I2C control registers */
#define EPIC_I2C_ADRS_REG 0x03000
#define EPIC_I2C_FDIV_REG 0x03004
#define EPIC_I2C_CTRL_REG 0x03008
#define EPIC_I2C_STAT_REG 0x0300C
#define EPIC_I2C_DATA_REG 0x03010
/* DMA interrupt registers */
#define EPIC_DMA0_VEC_PRI_REG 0x11040
#define EPIC_DMA0_DEST_REG 0x11050
#define EPIC_DMA1_VEC_PRI_REG 0x11060
#define EPIC_DMA1_DEST_REG 0x11070
/* message unit interrupt registers */
#define EPIC_I2O_VEC_PRI_REG 0x110c0
#define EPIC_I2O_DEST_REG 0x110d0
/* interrupt task priority register */
#define EPIC_CPU_CUR_TASK_PRI_REG 0x20080
/* cpu interrupt acknowledge register */
#define EPIC_CPU_IACK_REG 0x200a0
/* cpu end-of-interrupt register */
#define EPIC_CPU_EOI_REG 0x200b0
/* MPC107 bus frequency */
#undef MPC107_66 /* define for 66 MHz; now 100 MHz */
#ifdef __cplusplus
}
#endif
#endif /* INC_mpc107_h */