www.pudn.com > vxworks0108.rar > esf.h

#ifndef _INT_H 
#define _INT_H 
 
#include "type.h" 
 
#define _EXC_OFF_RES0	 	0x00000		/* reserved */ 
#define _EXC_OFF_RESET	 	0x00100		/* system reset */ 
#define _EXC_OFF_MACH	 	0x00200		/* machine check */ 
#define _EXC_OFF_DATA	 	0x00300		/* data access */ 
#define _EXC_OFF_INST	 	0x00400		/* instruction access */ 
#define _EXC_OFF_INTR	 	0x00500		/* external interrupt */ 
#define _EXC_OFF_ALIGN	 	0x00600		/* alignment */ 
#define _EXC_OFF_PROG	 	0x00700		/* program */ 
#define _EXC_OFF_FPU	 	0x00800		/* floating point unavailable */ 
#define _EXC_OFF_DECR	 	0x00900		/* decrementer */ 
#define _EXC_OFF_RES1	 	0x00a00		/* reserved */ 
#define _EXC_OFF_RES2	 	0x00b00		/* reserved */ 
#define _EXC_OFF_SYSCALL 	0x00c00		/* system call */ 
#define _EXC_OFF_TRACE	 	0x00d00		/* trace */ 
#define _EXC_OFF_RES3	 	0x00e00		/* reserved */ 
						/* exception for PPC601) */ 
 
/* 
 * Flags in MSR: 
 */ 
#define MSR_SF		(1<<63) 
#define MSR_ISF		(1<<61) 
#define MSR_VEC		(1<<25)		/* Enable AltiVec */ 
#define MSR_POW		(1<<18)		/* Enable Power Management */ 
#define MSR_WE		(1<<18)		/* Wait State Enable */ 
#define MSR_TGPR	(1<<17)		/* TLB Update registers in use */ 
#define MSR_CE		(1<<17)		/* Critical Interrupt Enable */ 
#define MSR_ILE		(1<<16)		/* Interrupt Little Endian */ 
#define MSR_EE		(1<<15)		/* External Interrupt Enable */ 
#define MSR_PR		(1<<14)		/* Problem State / Privilege Level */ 
#define MSR_FP		(1<<13)		/* Floating Point enable */ 
#define MSR_ME		(1<<12)		/* Machine Check Enable */ 
#define MSR_FE0		(1<<11)		/* Floating Exception mode 0 */ 
#define MSR_SE		(1<<10)		/* Single Step */ 
#define MSR_DWE		(1<<10)		/* Debug Wait Enable (4xx) */ 
#define MSR_BE		(1<<9)		/* Branch Trace */ 
#define MSR_DE		(1<<9) 		/* Debug Exception Enable */ 
#define MSR_FE1		(1<<8)		/* Floating Exception mode 1 */ 
#define MSR_IP		(1<<6)		/* Exception prefix 0x000/0xFFF */ 
#define MSR_IR		(1<<5) 		/* Instruction Relocate */ 
#define MSR_DR		(1<<4) 		/* Data Relocate */ 
#define MSR_PE		(1<<3)		/* Protection Enable */ 
#define MSR_PX		(1<<2)		/* Protection Exclusive Mode */ 
#define MSR_RI		(1<<1)		/* Recoverable Exception */ 
#define MSR_LE		(1<<0) 		/* Little Endian */ 
 
 
 
/* 
 *  Interrupt and trap vectors. 
 */ 
 
#define	EX_BEGIN	0x0000		/* 0, First vector            */ 
#define	EX_RESV0	0x0000		/* 0, reserved                */ 
#define	EX_RESET	0x0100		/* 1, reset                   */ 
#define	EX_MCHEK	0x0200		/* 2, machine check           */ 
#define	EX_DSI		0x0300		/* 3, data exception          */ 
#define	EX_ISI		0x0400		/* 4, instruction exception   */ 
#define	EX_EINT		0x0500		/* 5, external interrupt      */ 
#define	EX_ALIGN	0x0600		/* 6, memory access alignment */ 
#define	EX_PRGM		0x0700		/* 7, program exception       */ 
#define	EX_NOFP		0x0800		/* 8, FP unavailable          */ 
#define	EX_DECR		0x0900		/* 9, Decrementer             */ 
#define	EX_RESVA	0x0a00		/* a, reserved                */ 
#define	EX_RESVB	0x0b00		/* b, reserved                */ 
#define	EX_SC		0x0c00		/* c, System Call             */ 
#define	EX_TRACE	0x0d00		/* d, Program trace           */ 
#define EX_FPA		0x0e00		/* e, FP Assist               */ 
#define	EX_PERF		0x0f00		/* f, Performance monito      */ 
#define	EX_RESV10	0x1000		/* 10, reserved               */ 
#define	EX_RESV11	0x1100		/* 11, reserved               */ 
#define	EX_RESV12	0x1200		/* 12, reserved               */ 
#define	EX_IABP		0x1300		/* 13, Instruction BP         */ 
#define	EX_SMI		0x1400		/* 14, System Management      */ 
#define	EX_END		0x2f00		/* Last                       */ 
 
/* upper Machine State Register (MSR) mask */ 
 
#define _PPC_MSR_SF_U		0x8000	/* sixty-four bit mode (not  
					 * implemented for 32-bit machine) */ 
#define _PPC_MSR_POW_U		0x0004	/* power managemnet enable */  
#define _PPC_MSR_ILE_U		0x0001	/* little endian mode */ 
 
/* lower Machine State Register (MSR) mask */ 
 
#define	_PPC_MSR_EE		0x8000	/* external interrupt enable */ 
#define _PPC_MSR_PR		0x4000	/* privilege level */ 
#define _PPC_MSR_FP		0x2000	/* floating-point available */ 
#define _PPC_MSR_ME		0x1000	/* machine check enable  */ 
#define _PPC_MSR_FE0		0x0800	/* floating-point exception mode 0 */ 
#define _PPC_MSR_SE		0x0400	/* single-step trace enable */ 
#define _PPC_MSR_BE		0x0200	/* branch trace enable */ 
#define _PPC_MSR_FE1		0x0100	/* floating-point exception mode 1 */ 
#define _PPC_MSR_IP		0x0040	/* exception prefix */ 
#define _PPC_MSR_IR		0x0020	/* instruction address translation */ 
#define _PPC_MSR_DR		0x0010	/* data address translation */ 
#define _PPC_MSR_RI		0x0002	/* recoverable interrupt */ 
#define _PPC_MSR_LE		0x0001	/* little-endian mode */ 
 
#define _PPC_MSR_POWERUP	0x0040	/* state of MSR at powerup */ 
 
/* MSR bit definitions common to all PPC arch. */ 
 
#define _PPC_MSR_BIT_EE		16	/* MSR Ext. Intr. Enable bit - EE */ 
#define _PPC_MSR_BIT_PR		17	/* MSR Privilege Level bit - PR */ 
#define _PPC_MSR_BIT_ME		19	/* MSR Machine Check Enable bit - ME */ 
#define _PPC_MSR_BIT_LE		31	/* MSR Little Endian mode bit - LE */ 
 
/* FPSCR bit definitions (valid for the PPC60X familly) */ 
 
#define _PPC_FPSCR_FX           0x80000000 /* FP exception summary */ 
#define _PPC_FPSCR_FEX          0x40000000 /* FP enabled exception summary */ 
#define _PPC_FPSCR_VX           0x20000000 /* FP invalid exception summary */ 
#define _PPC_FPSCR_OX           0x10000000 /* FP overflow exception */ 
#define _PPC_FPSCR_UX           0x08000000 /* FP underflow exception */ 
#define _PPC_FPSCR_ZX           0x04000000 /* FP divide by zero exception */ 
#define _PPC_FPSCR_XX           0x02000000 /* FP inexact exception */ 
#define _PPC_FPSCR_VXSNAN       0x01000000 /* FP invalid exception for SNAN */ 
#define _PPC_FPSCR_VXISI        0x00800000 /* FP invalid exc. for INF-INF */ 
#define _PPC_FPSCR_VXIDI        0x00400000 /* FP invalid exc. for INF/INF */ 
#define _PPC_FPSCR_VXZDZ        0x00200000 /* FP invalid exc. for 0/0 */ 
#define _PPC_FPSCR_VXIMZ        0x00100000 /* FP invalid exc. for INF*0 */ 
#define _PPC_FPSCR_VXVC         0x00080000 /* FP inval. exc. for invalid comp.*/ 
#define _PPC_FPSCR_FR           0x00040000 /* FP fraction rounded */ 
#define _PPC_FPSCR_FI           0x00020000 /* FP fraction inexact */ 
#define _PPC_FPSCR_FPRF         0x0001F000 /* FP result flags */ 
#define _PPC_FPSCR_VXSOFT       0x00000400 /* FP inval. exc. for soft. request*/ 
#define _PPC_FPSCR_VXSQRT       0x00000200 /* FP inval. exc. for sqrt */ 
#define _PPC_FPSCR_VXCVI        0x00000100 /* FP inval. exc. for int convert */ 
#define _PPC_FPSCR_VE           0x00000080 /* FP invalid exc. enable */ 
#define _PPC_FPSCR_OE           0x00000040 /* FP overflow exc. enable */ 
#define _PPC_FPSCR_UE           0x00000020 /* FP underflow exc. enable */ 
#define _PPC_FPSCR_ZE           0x00000010 /* FP divide by zero exc. enable */ 
#define _PPC_FPSCR_XE           0x00000008 /* FP iinexact exc. enable */ 
#define _PPC_FPSCR_NI           0x00000004 /* FP non-IEEE mode enable */ 
#define _PPC_FPSCR_RN(n)        (n)        /* FP rounding control value */ 
 
#define _PPC_FPSCR_RN_MSK       0x00000003 /* FP rounding control bits mask */ 
#define _PPC_FPSCR_EXC_MASK     0x1ff80700 /* FP exception status bits mask */ 
#define _PPC_FPSCR_CTRL_MASK    0x000000ff /* FP exception control bits mask */ 
 
/* FPSCR init value for tasks spawned with VX_FP_TASK (PPC60X only) */ 
 
#define _PPC_FPSCR_INIT         (_PPC_FPSCR_OE | _PPC_FPSCR_UE | _PPC_FPSCR_ZE \ 
				 | _PPC_FPSCR_RN(0)) 
 
 
#ifndef _ASMLANGUAGE 
typedef	unsigned int	_RType;		/* default register type */ 
#endif 	/* _ASMLANGUAGE */ 
 
#define _ARCH_MULTIPLE_CACHELIB	FALSE 
 
#define	_DYNAMIC_BUS_SIZING	FALSE	/* require alignment for swap */ 
 
#define	_PPC_REG_SIZE		4	/* default register size */ 
 
#define _PPC_TEXT_SEG_ALIGN     4       /* 4 byte text segment alignment */ 
 
#ifndef _ASMLANGUAGE 
 
int excIntConnect (VOIDFUNCPTR * verbase, VOIDFUNCPTR  excHandle); 
 
void excVecInit(); 
 
#endif 
#endif