www.pudn.com > vxworks0108.rar > config.h
#ifndef _CONFIG_H
#define _CONFIG_H
#define DEFAULT_BOOT_LINE "dc(0,0)host:ucos h=90.0.0.1 e=90.0.0.2"
#define INCLUDE_CACHE_SUPPORT
#define USER_I_CACHE_ENABLE
#define INCLUDE_CACHE_L2
#define INCLUDE_L2_CACHE_ENABLE
#define INCLUDE_VME
#define INCLUDE_UNIVERSE /* Tundra universe support */
#define INCLUDE_VME_DMA /*include DMA support */
#define INCLUDE_VME_MBOX /* include mailbox support */
#define PCI_CFG_TYPE PCI_CFG_AUTO
#define ROM_TEXT_BASE 0x78080000
#define RAM_DST_ADRS 0x100000
#define STACK_ADRS _romInit
#define RAM_LOW_ADRS 0x100000
#define NV_RAM_ADRS NVSRAM_BASE_ADRS /* address of first non-volatile byte */
#define NV_RAM_INTRVL 1 /* address interval between bytes */
#define NV_RAM_SIZE NVSRAM_SIZE /* total number of bytes in device */
#undef NV_BOOT_OFFSET
#define NV_BOOT_OFFSET (NVSRAM_SIZE - 0x100) /* 0x100 - Offset to first byte of boot line information */
#define SM_ANCHOR_OFFSET 0x4100
#define BOOT_LINE_OFFSET 0x4200
#define EXC_MSG_OFFSET 0x4300
#define ROM_BASE_ADRS 0x78080000 /* base address of boot ROM */
#define ROM_SIZE 0x00180000 /* 512 kb ROM space */
#define ROM_TEXT_ADRS (ROM_BASE_ADRS + 0x0100) /* with PC & SP */
#define ROM_WARM_ADRS (ROM_TEXT_ADRS + 0x0004) /* warm reboot entry */
#define EXT_ROM_BASE_ADRS 0x78000000 /* base address of extended ROM */
#define EXT_ROM_SIZE 0x04000000 /* size of extended ROM (16-64meg) */
/*
* PMON/2000 entry points
*
* ROM_PMON_COLD_ADRS: PMON cold boot entry
* Complete PMON initilization.
* PMON starts searching for BDH's at sector 0 of extended flash.
*
* ROM_PMON_WARM_ADRS PMON extended flash boot entry
* PMON continues searching for BDH's.
*
*/
#define ROM_PMON_COLD_ADRS 0xfff00100 /* PMON cold boot entry */
#define ROM_PMON_WARM_ADRS 0xfff00110 /* PMON extended flash boot entry */
#define USER_RESERVED_MEM (0)
#define SM_ANCHOR_ADRS ((char *) (LOCAL_MEM_LOCAL_ADRS+SM_ANCHOR_OFFSET))
/* The bootroms put the boot line at the following address */
#define BOOT_LINE_ADRS ((char *) (LOCAL_MEM_LOCAL_ADRS+BOOT_LINE_OFFSET))
#define BOOT_LINE_SIZE 255 /* use 255 bytes for bootline */
/* Messages from exceptions during exceptions go at the following address */
#define EXC_MSG_ADRS ((char *) (LOCAL_MEM_LOCAL_ADRS+EXC_MSG_OFFSET))
/* Backplane H/W support */
#define SM_TAS_TYPE SM_TAS_HARD /* hardware supports test-and-set */
#define MEM_1MB 0x100000
#define MEM_16MB (16*MEM_1MB)
#define MEM_64MB (64*MEM_1MB)
#define MEM_256MB (256*MEM_1MB)
/* VME Master access windows, set size to 0 to disable a window */
#if defined (ADRS_MAP_PREP)
# define VME_A32_MSTR_BUS 0x08000000 /* Base VME address */
# define VME_A32_MSTR_SIZE 0x08000000 /* A32 master window size: 128 MB */
#else
# define VME_A32_MSTR_BUS 0x00000000 /* Base VME address */
# define VME_A32_MSTR_SIZE 0x40000000 /* A32 master window size: 1 GB */
#endif /* defined (ADRS_MAP_PREP) */
/* VME A24 master window, (16MB) */
#define VME_A24_MSTR_BUS 0x00000000 /* Base VME address */
#define VME_A24_MSTR_SIZE 0x01000000 /* 0 to 16MB, mult of 64K */
/* VME A16 Master window (64KB) */
#define VME_A16_MSTR_SIZE 0x00010000 /* either 0 or 64KB, only */
/* Setup VME slave windows, set size to 0 to disable a window */
/*
* VME A32 slave window, default is to map all local memory to VMEbus.
* The window size is set to LOCAL_MEM_SIZE. This will reduce the window
* size if LOCAL_MEM_SIZE does not reflect the actual amount of memory.
* Hence, if all of physical memory is to be addressed in the A32 window,
* the actual board memory size should be set in LOCAL_MEM_SIZE.
*/
#define VME_A32_SLV_LOCAL LOCAL_MEM_LOCAL_ADRS
#define VME_A32_SLV_BUS VME_A32_MSTR_BUS
#define VME_A32_SLV_SIZE (((ULONG)sysPhysMemTop()) - (LOCAL_MEM_LOCAL_ADRS))
/* VME A24 slave window, default is to not enable */
#define VME_A24_SLV_LOCAL LOCAL_MEM_LOCAL_ADRS
#define VME_A24_SLV_BUS VME_A24_MSTR_BUS
#undef A24_SLV_WINDOW /* #define to enable A24 slave window */
#if defined (A24_SLV_WINDOW)
# define VME_A24_SLV_SIZE VME_A24_MSTR_SIZE /* set to max, 16MB */
#else
# define VME_A24_SLV_SIZE 0x0 /* 0, window is disabled */
#endif /* defined (A24_SLV_WINDOW) */
/* VME A16 slave window, no default support */
#ifdef INCLUDE_VME_DMA
/* Default DMA operating parameters used by sysVmeDmaInit() */
/*
* VMEbus data transfer type
* - a combination of VMEbus Max. Datawidth (VDM) and
* VMEbus Cycle Type (VCT).
*
* choices:
* (DCTL_VDW_8 | DCTL_VCT_SINGLE)
* (DCTL_VDW_16 | DCTL_VCT_SINGLE)
* (DCTL_VDW_32 | DCTL_VCT_SINGLE)
* (DCTL_VDW_64 | DCTL_VCT_SINGLE)
* (DCTL_VDW_32 | DCTL_VCT_BLK) ** BLT **
* (DCTL_VDW_64 | DCTL_VCT_BLK) ** MBLT **
*/
#define VME_DMA_XFER_TYPE (DCTL_VDW_32 | DCTL_VCT_SINGLE)
/*
* VMEbus Address Space type
* choices:
* DCTL_VAS_A16
* DCTL_VAS_A24
* DCTL_VAS_A32
*/
#define VME_DMA_ADDR_SPACE DCTL_VAS_A32
/*
* Program/Data Address Modifier (AM) Code
* choices:
* DCTL_PGM_DATA
* DCTL_PGM_PRGM
*/
#define VME_DMA_DATA_TYPE DCTL_PGM_DATA
/*
* Supervisor/User Address Modifier (AM) Code
* choices:
* DCTL_SUPER_USER
* DCTL_SUPER_SUP
*/
#define VME_DMA_USER_TYPE DCTL_SUPER_SUP
/*
* VMEbus Aligned DMA Transfer Count (in bytes)
* - Max. data transferred before giving up the VMEbus
* choices:
* DGCS_VON_DONE
* DGCS_VON_256
* DGCS_VON_512
* DGCS_VON_1024
* DGCS_VON_2048
* DGCS_VON_4096
* DGCS_VON_8192
* DGCS_VON_16384
*/
#define VME_DMA_MAX_BURST DGCS_VON_DONE
/*
* Minimum period the DMA is off the VMEbus between tenures (in microseconds)
* choices:
* DGCS_VOFF_0
* DGCS_VOFF_16
* DGCS_VOFF_32
* DGCS_VOFF_64
* DGCS_VOFF_128
* DGCS_VOFF_256
* DGCS_VOFF_512
* DGCS_VOFF_1024
*/
#define VME_DMA_MIN_TIME_OFF_BUS DGCS_VOFF_0
#endif /* INCLUDE_VME_DMA */
#define SM_OFF_BOARD FALSE
#undef SM_ANCHOR_ADRS
#define SM_ANCHOR_ADRS ((sysProcNumGet() == 0) ? \
((char*) (LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET)) : \
((char*) (VME_A32_MSTR_LOCAL + SM_ANCHOR_OFFSET)))
#define SM_INT_TYPE SM_INT_MAILBOX_1 /* or SM_INT_NONE */
/*
* The following defines are only used by the master.
* If SM_OFF_BOARD == FALSE, these values are used
* by the master's UNIVERSE_II window definitions, so
* they need to be on a 64K byte boundary.
* The slave only uses the "Anchor" address.
*/
#define SM_MEM_ADRS 0x00010000 /* Start of actual SM region */
#define SM_MEM_SIZE 0x00020000
#define SM_OBJ_MEM_ADRS (SM_MEM_ADRS+SM_MEM_SIZE) /* SM Objects pool */
#define SM_OBJ_MEM_SIZE 0x00010000
#define LOCAL_MEM_AUTOSIZE /* undef for fixed size */
#define LOCAL_MEM_LOCAL_ADRS 0x00000000 /* fixed at zero */
#define LOCAL_MEM_SIZE 0x02000000 /* default memory size: 32MB */
/*
* These defines are used to initialize the External Source
* Vector/Priority registers in the EPIC. The following can
* be defined: interrupt sensitivity, polarity and interrupt priority.
*
* Note: by default a 1 into the sense bit(22) will setup for level
* sensitive, and a 0 into the polarity bit(23) will setup for low
* polarity.
*
* At initialization all external interrupt sources are disabled
* except for the 8259 input, which is enabled in the EPIC driver.
*
* All currently unused interrupt sources are set to a priority of
* 0, which will not allow them to be enabled. If any one of these
* levels is to be used, the priority value must be changed here.
*/
#define INIT_EXT_SRC0 ( INT_MASK_BIT | HIGH_POLARITY | LEVEL_SENSE |\
PRIORITY_LVL7 ) /* PIB (8259) */
#define INIT_EXT_SRC1 ( INT_MASK_BIT | LEVEL_SENSE |\
PRIORITY_LVL11 ) /* PCI INTA#: ethernet */
#define INIT_EXT_SRC2 ( INT_MASK_BIT | LEVEL_SENSE |\
PRIORITY_LVL10 ) /* PCI INTB#: Universe */
#define INIT_EXT_SRC3 ( INT_MASK_BIT | LEVEL_SENSE |\
PRIORITY_LVL9 ) /* PCI INTC#: SCSI, PMC2 (INTA#) */
#define INIT_EXT_SRC4 ( INT_MASK_BIT | LEVEL_SENSE |\
PRIORITY_LVL8 ) /* PCI INTD#: PMC1 (INTA#) */
/*
* These defines are used to initialize the global timer
* Vector/Priority registers in the EPIC. The following can
* be defined: interrupt priority, interrupt vector.
*
* At initialization all global timers are disabled.
*
*/
/* EPIC timer 0 */
#define INIT_GLOBAL_TIMER0 (INT_MASK_BIT | \
PRIORITY_LVL15 | \
EPIC_TIMER0_INT_VEC)
/* EPIC timer 1 */
#define INIT_GLOBAL_TIMER1 (INT_MASK_BIT | \
PRIORITY_LVL14 | \
EPIC_TIMER1_INT_VEC)
/* EPIC timer 2 */
#define INIT_GLOBAL_TIMER2 (INT_MASK_BIT | \
PRIORITY_LVL13 | \
EPIC_TIMER2_INT_VEC)
/* EPIC timer 3 */
#define INIT_GLOBAL_TIMER3 (INT_MASK_BIT | \
PRIORITY_LVL12 | \
EPIC_TIMER3_INT_VEC)
#endif