www.pudn.com > vxworks0108.rar > sysMaxL2Disable.s

/* sysMaxL2Disable.s - MPC7400 (MAX) L2 Cache Disable Route */


/*
DESCRIPTION
This module contains routines written in assembly language to address a
MAX processor cache errata.  The following is the response from SPS
regarding the problem:

The problem exists on all versions of the MPC7400 (MAX) processor and is 
not expected to be fixed.  A fix is targeted for revision 1.3 of the MPC7410 
(Nitro) processor.

Overview:

The MPC7400 can hang if the L2 is disabled during an outstanding instruction
fetch.

Detailed Description:

The problem centers around the interaction of the instruction cache and the
L2 cache as the L2 cache is disabled.  The scenario is as follows:

  1. An ifetch misses in the icache and allocates a reload table entry
  2. As the instructions return from the BIU they are forwarded around the
     icache and dispatched as well as written to the IRLDQ.
  3. One of these instruction is a mtspr targeting the L2CR.  This
     instruction  disables the L2.
  4. When all beats of data return to the IRLDQ, the IRLT arbitrates to
     reload the L2.  Since the L2 is now disabled, it does not expect reload
     requests from the IRLT.
  5. The unexpected reload request is mishandled by the L2 and passed to the
     BIU as an ifetch miss.

Workaround:
  1. Preload the code that disables the L2 into the instruction cache before
     execution.  This requires the code be structured in such a way that the
     instruction fetch be completed before the mtspr is executed.
*/

#define _ASMLANGUAGE

/* includes */

#include "config.h"
#include "reg.h"    
#include "asm.h"
#include "sysCache.h"

   .align  3

/* globals */

   .globl  sysMaxL2Disable        /* Max L2 disable routine */

/*******************************************************************************
*
* sysMaxL2Disable - MAX Disable L2 Cache function
*
* This routine disables the MAX L2 cache by first flushing the L2 using
* the hardware flush bit in SPR 1017, L2CR.  It then turns off the enable
* bit in L2CR.
*
* RETURNS: None
*/

sysMaxL2Disable:

   /* Instruction for dssall */

   .long 0x7E00066C    
   sync

   mfspr   r3,1017

   /* Hardware flush L2 */

   lis    r4,HI(MPC750_L2CR_HWF)
   ori    r4,r4,LO(MPC750_L2CR_HWF)
   or     r3,r3,r4
   mtspr  1017,r3          
   sync
   isync

   /* Disable the L2 cache */

   lis    r4,HI(MPC750_L2CR_E)
   ori    r4,r4,LO(MPC750_L2CR_E)
   mfspr  r3,1017
   andc   r3,r3,r4
   sync

   b preFetchL2DisableCode

codeIsPrefetched:
   mtspr  1017,r3          
   sync
   isync

   b pastFetchL2DisableCode

preFetchL2DisableCode:
   sync
   isync
   b codeIsPrefetched

pastFetchL2DisableCode:

   /* Return to caller */

   bclr    20,0