www.pudn.com > vxworks0108.rar > rom_debug.s
#ifndef _ROM_DEBUG_H
#define _ROM_DEBUG_H
#ifdef __cplusplus
extern "C" {
#endif
#if CONSOLE_TTY == 0
# define SDEBUG_COM M1543C_COM1_IO_ADRS
#else
# define SDEBUG_COM M1543C_COM2_IO_ADRS
#endif /* if CONSOLE_TTY == 0 */
#define BAUD_RATE 0x0c /* BAUD_RATE = (24MHz / 13) / (16 * 9600) */
/******************************************************************************
*
* romDebugInit -- intialize serial channel
*
* This routine initializes the pre-defined serial channel for the usage
* during rom initialization.
*
* input none
*
* usage
* r30 - base address of serial channel
* r31 - data and config values for serial channel
*
*/
romDebugInit:
isync
LOADREG (r30, SDEBUG_COM)
ori r31, r31, 0x00 /* no interrupts */
stb r31, 1(r30)
li r31, 0x03
stb r31, 3(r30) /* use 8 bit data len, DLAB=0 */
isync
li r31, 0x06
stb r31, 2(r30) /* reset tx and rx FIFO */
isync
li r31, 0x01
stb r31, 2(r30) /* enable FIFO and set DMA mode to 0 */
isync
li r31, 0x83
stb r31, 3(r30) /* set DLAB */
isync
li r31, BAUD_RATE /* write the baudrate LSB */
stb r31, 0(r30)
isync
li r31, 0x00
stb r31, 1(r30) /* write baudrate MSB */
isync
li r31, 0x03
stb r31, 3(r30) /* use 8 bit data len */
isync
li r31, 0x03
stb r31, 4(r30) /* set RTS and DTR (interrupts disabled) */
isync
blr
/******************************************************************************
*
* romPutc -- output a character
*
* This routine output a character to console
*
* input r31 --> character to output
*
* usage r30
*
*/ .globl romPutc
.align 2
romPutc:
isync
LOADREG (r30, SDEBUG_COM)
addi r30, r30, 5
lbz r30, 0(r30)
rlwinm r30, r30, 0, 26, 26 /* test the THRE reg */
cmpi 0, 0, r30, 0 /* poll bit until char is ready */
bc 12, 2, romPutc # eq
isync
LOADREG (r30, SDEBUG_COM)
stb r31, 0(r30)
isync
nop
nop
nop
blr
/******************************************************************************
*
* romPuts -- output a string
*
* This routine output a string to console, until null terminated.
*
* input r3 --> msg ptr, point to RAM (GNU tool locate to edata area,
* this area is not initialized), so it is adjusted by this routine
* to point to FLASH.
*
* usage r0, r3, r31
*
* NOTE: the stack may not be initialized,
* so the return address is saved at r0
*/ .globl romPuts
romPuts:
mfspr r0, LR /* save return in r0 */
LOADREG (r31, romInit)
sub r3, r3, r31
LOADREG (r31, ROM_TEXT_ADRS)
add r3, r3, r31
puts1:
lbz r31,0(r3) /* load char */
cmpli 0, 0, r31, 0 /* NULL */
beq putsexit /* exit */
bl romPutc
addi r3, r3, 1 /* next char */
b puts1
putsexit:
mtspr LR, r0
blr
#ifdef __cplusplus
}
#endif
#endif /* ifndef _ROM_DEBUG_H */