www.pudn.com > 1553_enc_dec.rar > test_1553.v

// ============================================================================= 
//                           COPYRIGHT NOTICE 
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation 
// 
// Permission : 
//  
// Lattice Semiconductor grants permission to use this code for use in synthesis 
// for Lattice programmable logic product. Other use of this code, including  
// the selling or duplication of any portion ia strictly prohibited. 
//  
// Disclaimer : 
// 
// This VHDL or Verilog source code is intended as a design reference which 
// illustrares how these types of functions can be implemeted. It is the  
// user's responsibility to verify their design for consistency and  
// functionality through the use of formal verification methods.  
// Lattice Semiconductor provides no waranty regarding the use or  
// functionality of this code.  
// ============================================================================= 
// 
//                     Lattice Semiconductor Corporation     
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//                     Hillsboro, OR 97124                   
//                     U.S.A                                
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// ============================================================================= 
// Project          : 1553_enc_dec 
// File             : test_1553.v 
// Title            :  
// Dependencies     : encoder_1553.v 
//                    decoder_1553.v  
// Description      : This is a simple non-automated test bench to test 
//                    1553 encoder and decoder connected to eachother. 
//                    Look for generated waveform file "test_1553.trn"  
// ============================================================================= 
// REVISION HISTORY 
// Version          : 1.0 
// ============================================================================= 
 
module test_1553 (); 
 
 
reg        enc_clk ; 
reg        dec_clk ; 
reg        rst_n ; 
reg [15:0] tx_dword ; 
reg        tx_csw ; 
reg        tx_dw ; 
 
wire       tx_data ; 
wire       tx_dval ; 
wire       serial_data ; 
 
encoder_1553 u1_encoder ( 
            // Clock and Reset 
            .enc_clk    ( enc_clk ), 
            .rst_n      ( rst_n ), 
 
            // Inputs 
            .tx_dword   ( tx_dword ), 
            .tx_csw     ( tx_csw ), 
            .tx_dw      ( tx_dw ), 
 
            // Outputs 
            .tx_busy    ( ), 
            .tx_data    ( tx_data ),  
            .tx_dval    ( tx_dval ) 
            ) ; 
 
assign serial_data = (tx_data & tx_dval) ; 
 
decoder_1553 u1_decoder ( 
            // Clock and Reset 
            .dec_clk    ( dec_clk ), 
            .rst_n      ( rst_n ), 
 
            // Inputs 
            .rx_data    ( serial_data ), 
 
            // Outputs 
            .rx_dword   ( ),  
            .rx_dval    ( ), 
            .rx_csw     ( ), 
            .rx_dw      ( ), 
            .rx_perr    ( ) 
            ) ; 
 
 
initial begin 
   enc_clk  <= 1'b0 ; 
   dec_clk  <= 1'b0 ; 
   rst_n    <= 1'b0 ; 
   tx_dword <= 16'd0 ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b0 ; 
end 
 
always #500 enc_clk = ~enc_clk ; 
always #125 dec_clk = ~dec_clk ; 
 
initial begin 
   repeat (10) @(posedge enc_clk) ; 
   rst_n   <= 1'b1 ; 
 
   repeat (39) @(posedge enc_clk) ; 
   tx_dword <= 16'h5555 ; 
   tx_csw   <= 1'b1 ; 
   tx_dw    <= 1'b0 ; 
   repeat (1) @(posedge enc_clk) ; 
   tx_dword <= 16'h0000 ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b0 ; 
 
   repeat (39) @(posedge enc_clk) ; 
   tx_dword <= 16'hABCD ; 
   tx_csw   <= 1'b1 ; 
   tx_dw    <= 1'b0 ; 
   repeat (1) @(posedge enc_clk) ; 
   tx_dword <= 16'h0000 ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b0 ; 
 
   repeat (39) @(posedge enc_clk) ; 
   tx_dword <= 16'hFFFF ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b1 ; 
   repeat (1) @(posedge enc_clk) ; 
   tx_dword <= 16'h0000 ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b0 ; 
 
   repeat (39) @(posedge enc_clk) ; 
   tx_dword <= 16'h1234 ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b1 ; 
   repeat (1) @(posedge enc_clk) ; 
   tx_dword <= 16'h0000 ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b0 ; 
 
   repeat (5) @(posedge enc_clk) ; 
   repeat (39) @(posedge enc_clk) ; 
   tx_dword <= 16'h5678 ; 
   tx_csw   <= 1'b1 ; 
   tx_dw    <= 1'b0 ; 
   repeat (1) @(posedge enc_clk) ; 
   tx_dword <= 16'h0000 ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b0 ; 
 
   repeat (5) @(posedge enc_clk) ; 
   repeat (39) @(posedge enc_clk) ; 
   tx_dword <= 16'hAAAA ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b1 ; 
   repeat (1) @(posedge enc_clk) ; 
   tx_dword <= 16'h0000 ; 
   tx_csw   <= 1'b0 ; 
   tx_dw    <= 1'b0 ; 
 
 
   repeat (100) @(posedge enc_clk) ; 
   $display("---INFO : Simulation Ended, Check waveform"); 
   $finish ; 
end 
 
/* 
initial begin 
   $recordfile ("test_1553.trn"); 
   $recordvars (); 
end 
*/ 
 
endmodule