www.pudn.com > 1553_enc_dec.rar > encoder_1553.prf

SCHEMATIC START ; 
# map:  version ispLever_v41_Production_Build_Classic (16c) -- Mon Jun 28 12:35:38 2004 
 
SCHEMATIC END ; 
# 
# Logical Preferences generated for Lucent by Synplify 7.3.5, Build 267R. 
# 
# Period Constraints 
FREQUENCY PORT "enc_clk" 2.000000 MHz ; 
# Output Constraints 
CLOCK_TO_OUT PORT "tx_busy" 450.000000 ns CLKPORT "enc_clk" ; 
CLOCK_TO_OUT PORT "tx_data" 450.000000 ns CLKPORT "enc_clk" ; 
CLOCK_TO_OUT PORT "tx_dval" 450.000000 ns CLKPORT "enc_clk" ; 
# Input Constraints 
INPUT_SETUP PORT "tx_dword_15" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_14" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_13" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_12" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_11" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_10" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_9" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_8" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_7" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_6" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_5" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_4" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_3" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_2" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_1" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dword_0" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_csw" 450.000000 ns CLKPORT "enc_clk" ; 
INPUT_SETUP PORT "tx_dw" 450.000000 ns CLKPORT "enc_clk" ; 
#Begin false path from constraints 
BLOCK PATH FROM PORT "rst_n" ; 
#End false path from constrains 
BLOCK ASYNCPATHS ; 
# End of generated Logical Preferences. 
COMMERCIAL ;