www.pudn.com > 1553_enc_dec.rar > decoder_1553.prf

SCHEMATIC START ; 
# map:  version ispLever_v41_Production_Build_Classic (16c) -- Mon Jun 28 12:31:57 2004 
 
SCHEMATIC END ; 
# 
# Logical Preferences generated for Lucent by Synplify 7.3.5, Build 267R. 
# 
# Period Constraints 
FREQUENCY PORT "dec_clk" 10.000000 MHz ; 
# Output Constraints 
CLOCK_TO_OUT PORT "rx_dword_15" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_14" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_13" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_12" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_11" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_10" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_9" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_8" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_7" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_6" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_5" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_4" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_3" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_2" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_1" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dword_0" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dval" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_csw" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_dw" 50.000000 ns CLKPORT "dec_clk" ; 
CLOCK_TO_OUT PORT "rx_perr" 50.000000 ns CLKPORT "dec_clk" ; 
# Input Constraints 
INPUT_SETUP PORT "rx_data" 50.000000 ns CLKPORT "dec_clk" ; 
#Begin false path from constraints 
BLOCK PATH FROM PORT "rst_n" ; 
#End false path from constrains 
BLOCK ASYNCPATHS ; 
# End of generated Logical Preferences.