www.pudn.com > dsp-code.rar > Inverter1002.c, change:2013-12-02,size:8497b


/* 
 * Inverter1002.c 
 * 	发出12路PWM波形,两两互补 
 * 	16路 ADC采样 
 */ 
#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File 
 
interrupt void EPWM1_ISR(void); 
interrupt void ADC_ISR(void); 
void ConfigureGPIO18(void); 
void ConfigureEPWMn(void); 
void ConfigureADC(void); 
volatile unsigned long InterruptedTimes; 
volatile unsigned long ADCedTimes; 
volatile unsigned int ADCResults[16]; 
 
void main(void){ 
	InitSysCtrl();//PLL,WatchDog,Peripheral Clocks, 100M 
	InitEPwmGpio();//All EPWMx(1-6)n(A,B) pins Configured as OutPut GPIO, EPWM 
	InitAdc();//Initialize ADC Module 
	ConfigureGPIO18(); 
	DINT;//Disable Interrupts 
	InitPieCtrl();//Initialize the PIE control registers 
	IER = 0x0000;//Disable CPU interrupts 
	IFR = 0x0000;//Clear all CPU interrupt flags 
	InitPieVectTable();//Initialize the PIE vector table with pointers to the shell Interrupt 
 
	EALLOW;  // This is needed to write to EALLOW protected register 
	PieVectTable.ADCINT = &ADC_ISR; 
	EDIS;    // This is needed to disable write to EALLOW protected registers 
	ConfigureADC(); 
	IER |= M_INT1; // Enable CPU Interrupt 1 
	PieCtrlRegs.PIEIER1.bit.INTx6 = 1; 
 
	EALLOW;  // This is needed to write to EALLOW protected registers 
	PieVectTable.EPWM1_INT = &EPWM1_ISR; 
	EDIS;    // This is needed to disable write to EALLOW protected registers 
	ConfigureEPWMn();//Configure EPWMs 
	IER |= M_INT3;//Enable Group3 Interrupt 
	PieCtrlRegs.PIEIER3.bit.INTx1 = 1;//Group3 INT1 -> EPWM1 enable 
	// Enable global Interrupts and higher priority real-time debug events: 
	EINT;   // Enable Global interrupt INTM 
	ERTM;   // Enable Global realtime interrupt DBGM 
 
	InterruptedTimes = 0; 
	ADCedTimes = 0; 
	while(1){ 
	} 
} 
 
interrupt void EPWM1_ISR(void){ 
	InterruptedTimes ++; 
	if((InterruptedTimes % 10000) == 0){ 
		GpioDataRegs.GPATOGGLE.bit.GPIO18 = 1; 
	} 
	EPwm1Regs.ETCLR.bit.INT = 1;//Clear flag 
	PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; 
} 
 
interrupt void ADC_ISR(void){ 
	ADCedTimes ++; 
	ADCResults[0] = AdcRegs.ADCRESULT0>>4;//ADCA0 
	ADCResults[1] = AdcRegs.ADCRESULT1>>4;//ADCA1 
	ADCResults[2] = AdcRegs.ADCRESULT2>>4;//ADCA2 
	ADCResults[3] = AdcRegs.ADCRESULT3>>4;//ADCA3 
	ADCResults[4] = AdcRegs.ADCRESULT4>>4;//ADCA4 
	ADCResults[5] = AdcRegs.ADCRESULT5>>4;//ADCA5 
	ADCResults[6] = AdcRegs.ADCRESULT6>>4;//ADCA6 
	ADCResults[7] = AdcRegs.ADCRESULT7>>4;//ADCA7 
	ADCResults[8] = AdcRegs.ADCRESULT8>>4;//ADCB0 
	ADCResults[9] = AdcRegs.ADCRESULT9>>4;//ADCB1 
	ADCResults[10] = AdcRegs.ADCRESULT10>>4;//ADCB2 
	ADCResults[11] = AdcRegs.ADCRESULT11>>4;//ADCB3 
	ADCResults[12] = AdcRegs.ADCRESULT12>>4;//ADCB4 
	ADCResults[13] = AdcRegs.ADCRESULT13>>4;//ADCB5 
	ADCResults[14] = AdcRegs.ADCRESULT14>>4;//ADCB6 
	ADCResults[15] = AdcRegs.ADCRESULT15>>4;//ADCB7 
	// Reinitialize for next ADC sequence 
	AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1 
	AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit 
	PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE 
} 
 
void ConfigureGPIO18(void){ 
	EALLOW; 
	GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; 
	GpioCtrlRegs.GPADIR.bit.GPIO18 = 1;//Output GPIO18 
	EDIS; 
} 
 
#define EPWM1_TIMER_TBPRD 50002 
void ConfigureEPWMn(void){ 
	EALLOW; 
	SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;//Disable Clock 
	EDIS; 
 
	// Setup TBCLK 
	EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 7500, Frequency equals 150M/2/7500 = 10K 
	EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 
	EPwm1Regs.TBCTR = 0x0000;            // Clear counter 
	// Set Compare values 
	EPwm1Regs.CMPA.half.CMPA = 1000;     // Set compare A value 
	EPwm1Regs.CMPB = 1000;               // Set Compare B value 
	// Setup counter mode 
	EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up 
	EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading 
	EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;         // Load from shadow register 
	EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; 
	EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;		   // Clock ratio = SYSCLKOUT/HSPCLKDIV/CLKDIV 
    // Setup shadowing 
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Shadow Mode 
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; 
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // Load on Zero 
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; 
    // Set actions 
    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;             // Set PWM1A on event A, up count 
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;           // Clear PWM1A on event A, down count 
    //EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;             // Set PWM1B on event B, up count 
    //EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;           // Clear PWM1B on event B, down count 
 
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; 
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;	  // Toggle EPWM1B only 
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;		  // Delay on Raising and Falling 
    EPwm1Regs.DBRED = 100;						  // Falling Edge Delay = 150 TBCLKs 
    EPwm1Regs.DBFED = 100;						  // Raising Edge Delay = 150 TBCLKs 
 
    // Interrupt where we will change the Compare Values 
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;      // Select INT on Zero event 
    EPwm1Regs.ETSEL.bit.INTEN = 1;	               // Enable INT 
    EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;            // Generate INT on 3rd event 
 
    //trigger SOC 
    EPwm1Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group 
    EPwm1Regs.ETSEL.bit.SOCASEL = 1;       // Select SOC from ZERO 
    EPwm1Regs.ETPS.bit.SOCAPRD = 1;        // Generate pulse on 1st event 
 
    // Setup TBCLK 
    EPwm4Regs.TBPRD = EPWM1_TIMER_TBPRD;           // Set timer period 5000, Frequency equals 100M/2/5000 = 10K 
    EPwm4Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0 
    EPwm4Regs.TBCTR = 0x0000;                      // Clear counter 
    // Set Compare values 
    EPwm4Regs.CMPA.half.CMPA = 1000;     // Set compare A value 
    EPwm4Regs.CMPB = 1000;               // Set Compare B value 
    // Setup counter mode 
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up 
    EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading 
    EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;         // Load from shadow register 
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; 
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;		   // Clock ratio = SYSCLKOUT/HSPCLKDIV/CLKDIV 
    // Setup shadowing 
    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Shadow Mode 
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; 
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // Load on Zero 
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; 
    // Set actions 
    EPwm4Regs.AQCTLA.bit.CAU = AQ_SET;             // Set PWM1A on event A, up count 
    EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;           // Clear PWM1A on event A, down count 
    //EPwm4Regs.AQCTLB.bit.CBU = AQ_SET;             // Set PWM1B on event B, up count 
    //EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR;           // Clear PWM1B on event B, down count 
 
    EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; 
    EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;	  // Toggle EPwm4B only 
    EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;		  // Delay on Raising and Falling 
    EPwm4Regs.DBRED = 100;						  // Falling Edge Delay = 150 TBCLKs 
    EPwm4Regs.DBFED = 100;						  // Raising Edge Delay = 150 TBCLKs 
 
	EALLOW; 
	SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;//Enable Clock 
	EDIS; 
} 
 
void ConfigureADC(void){ 
	// Configure ADC Using Sequential Sampling Mode 
    AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Setup cascaded sequencer mode 
    AdcRegs.ADCMAXCONV.all = 0x000F;    // 16 CONV 
    AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; 
    AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; 
    AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; 
    AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; 
    AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; 
    AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; 
    AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; 
    AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; 
    AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8; 
    AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9; 
    AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xA; 
    AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xB; 
    AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xC; 
    AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xD; 
    AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0xE; 
    AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0xF; 
    AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Started by ePWMx SOCA trigger 
    AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;  // Enable SEQ1 interrupt (every EOS) 
}