www.pudn.com > beipin_quartII.rar > bp2.vhd

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
entity bp2 is 
port (clk : in std_logic; 
   indata : in std_logic; 
   indatb : in std_logic; 
	    y : out std_logic); 
end bp2; 
ARCHITECTURE a of bp2 IS 
	SIGNAL b : STD_LOGIC; 
	SIGNAL c : STD_LOGIC; 
	SIGNAL d : STD_LOGIC; 
	SIGNAL e : STD_LOGIC; 
	SIGNAL f : STD_LOGIC; 
	SIGNAL g : STD_LOGIC; 
BEGIN 
	Process (clk) 
	begin 
	if clk 'event and clk='1' then 
	b<=indata; 
	end if; 
	if clk 'event and clk='1' then 
	c<=b; 
	end if; 
	end process; 
	Process (clk) 
	begin 
	if clk 'event and clk='1' then 
	d<=indatb; 
	end if; 
	if clk 'event and clk='1' then 
	e<=d; 
	end if; 
	end process; 
	f<=b xor c; 
	g<=d xor e; 
	y<=f or g; 
END a;