www.pudn.com > beipin_quartII.rar > bp2.map.eqn

-- Copyright (C) 1991-2006 Altera Corporation 
-- Your use of Altera Corporation's design tools, logic functions  
-- and other software and tools, and its AMPP partner logic  
-- functions, and any output files any of the foregoing  
-- (including device programming or simulation files), and any  
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License  
-- Subscription Agreement, Altera MegaCore Function License  
-- Agreement, or other applicable license agreement, including,  
-- without limitation, that your use is for the sole purpose of  
-- programming logic devices manufactured by Altera and sold by  
-- Altera or its authorized distributors.  Please refer to the  
-- applicable agreement for further details. 
--d is d 
d_or_out = indatb; 
d_reg_input = d_or_out; 
d = DFFE(d_reg_input, GLOBAL(clk), , , ); 
 
 
--b is b 
b_or_out = indata; 
b_reg_input = b_or_out; 
b = DFFE(b_reg_input, GLOBAL(clk), , , ); 
 
 
--c is c 
c_or_out = b; 
c_reg_input = c_or_out; 
c = DFFE(c_reg_input, GLOBAL(clk), , , ); 
 
 
--e is e 
e_or_out = d; 
e_reg_input = e_or_out; 
e = DFFE(e_reg_input, GLOBAL(clk), , , ); 
 
 
--A1L9 is y~5 
A1L9_p1_out = c & !b; 
A1L9_p2_out = !c & b; 
A1L9_p3_out = d & !e; 
A1L9_p4_out = !d & e; 
A1L9_or_out = A1L9_p1_out # A1L9_p2_out # A1L9_p3_out # A1L9_p4_out; 
A1L9 = A1L9_or_out; 
 
 
--clk is clk 
--operation mode is input 
 
clk = INPUT(); 
 
 
--indata is indata 
--operation mode is input 
 
indata = INPUT(); 
 
 
--indatb is indatb 
--operation mode is input 
 
indatb = INPUT(); 
 
 
--y is y 
--operation mode is output 
 
y = OUTPUT(A1L9);