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-- MAX+plus II VHDL Template 
-- Clearable loadable enablable counter 
 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
 
 
ENTITY div IS 
    port   (clk_input		: in	std_logic; 
		    compare		    : out	std_logic	); 
	 
END div; 
 
ARCHITECTURE a OF  div IS 
 
signal	cnt:  std_logic_vector(3 downto 0); 
signal  compare_temp: std_logic; 
	 
BEGIN 
 
	PROCESS (clk_input) is 
	BEGIN 
	  if (clk_input'event and clk_input='1') 
        then 
          if cnt="1111" then cnt<="0000"; 
          else 
             cnt <= cnt+1; 
          end if; 
      end if;  
    END process; 
    
   process (clk_input) is 
   begin 
     if (clk_input'event and clk_input='1') 
       then 
         if cnt(2 downto 0)="000" then 
            compare_temp <= not compare_temp; 
         end if; 
     end if; 
   end  process; 
   compare <= compare_temp; 
end a;