www.pudn.com > xc9572_1.rar > countest.tbw

info x 38 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
radix x 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 count4
term mark 34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

var add 4 0 0 226 15 0 257 100 50 50 10 10 0 0 0 0 CCLKInstd_logicRISING_EDGECCLK
var add 1 0 0 98 12 0 257 100 50 50 10 10 0 0 0 0 CEInstd_logicRISING_EDGECCLK
var add 2 0 0 98 13 0 257 100 50 50 10 10 0 0 0 0 CLRInstd_logicRISING_EDGECCLK
var add 3 1 0 100 14 0 257 100 50 50 10 10 0 0 0 0 UPInstd_logic_vectorRISING_EDGECCLK
var add 5 3 0 100 16 0 257 100 50 50 10 10 0 0 0 0 QoutOutstd_logic_vectorRISING_EDGECCLK
vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
npos xxx 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
cell fill 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cell fill 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
cell fill 3 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cell fill 3 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cell fill 3 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
cell fill 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
cell fill 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
cell fill 4 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
cell fill 4 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
cell fill 4 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11
cell fill 4 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11
cell fill 4 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10
cell fill 4 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
cell fill 4 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
time info 10 10 10 10 50 50 1 1 0 0 0 0 0 0 0 0 nsCCLK
font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
src mod 0 1443057802 29779999 0 0 0 0 0 0 0 0 0 0 0 0 0 count4.vhdl
utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
cellenab on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
grid on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
com add 1 1 0 161 7 0 -75 0 0 0 0 0 0 0 0 0 Waveform created by 
HDL Bencher 6.1i 
Source = count4.vhdl 
Tue Apr 25 11:33:49 2006
opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
NumClocks x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
clock_1 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCLK
Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.00000000000000