www.pudn.com > xc9572_1.rar > countest.ANT

-- D:\FPGA\XC_9572 
-- VHDL Annotation Test Bench created by 
-- HDL Bencher 6.1i 
-- Tue Apr 25 13:02:02 2006 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL; 
USE STD.TEXTIO.ALL; 
 
ENTITY countest IS 
END countest; 
 
ARCHITECTURE testbench_arch OF countest IS 
-- If you get a compiler error on the following line, 
-- from the menu do Options->Configuration select VHDL 87 
FILE RESULTS: TEXT OPEN WRITE_MODE IS "d:\fpga\xc_9572\countest.ano"; 
	COMPONENT count4 
		PORT ( 
			CE : In  std_logic; 
			CLR : In  std_logic; 
			UP : In  std_logic_vector (1 DOWNTO 0); 
			CCLK : In  std_logic; 
			Qout : Out  std_logic_vector (3 DOWNTO 0) 
		); 
	END COMPONENT; 
 
	SIGNAL CE : std_logic; 
	SIGNAL CLR : std_logic; 
	SIGNAL UP : std_logic_vector (1 DOWNTO 0); 
	SIGNAL CCLK : std_logic; 
	SIGNAL Qout : std_logic_vector (3 DOWNTO 0); 
 
BEGIN 
	UUT : count4 
	PORT MAP ( 
		CE => CE, 
		CLR => CLR, 
		UP => UP, 
		CCLK => CCLK, 
		Qout => Qout 
	); 
 
	PROCESS -- clock process for CCLK, 
		VARIABLE TX_TIME : INTEGER :=0; 
 
		PROCEDURE ANNOTATE_Qout( 
			TX_TIME : INTEGER 
		) IS 
			VARIABLE TX_STR : String(1 to 4096); 
			VARIABLE TX_LOC : LINE; 
		BEGIN 
			STD.TEXTIO.write(TX_LOC,string'("Annotate[")); 
			STD.TEXTIO.write(TX_LOC, TX_TIME); 
			STD.TEXTIO.write(TX_LOC,string'(",Qout,")); 
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Qout); 
			STD.TEXTIO.write(TX_LOC, string'("]")); 
			TX_STR(TX_LOC.all'range) := TX_LOC.all; 
			STD.TEXTIO.writeline(results, TX_LOC); 
			STD.TEXTIO.Deallocate(TX_LOC); 
		END; 
 
	BEGIN 
		CLOCK_LOOP : LOOP 
		CCLK <= transport '0'; 
		WAIT FOR 10 ns; 
		TX_TIME := TX_TIME + 10; 
		CCLK <= transport '1'; 
		WAIT FOR 10 ns; 
		TX_TIME := TX_TIME + 10; 
		ANNOTATE_Qout(TX_TIME); 
		WAIT FOR 40 ns; 
		TX_TIME := TX_TIME + 40; 
		CCLK <= transport '0'; 
		WAIT FOR 40 ns; 
		TX_TIME := TX_TIME + 40; 
		END LOOP CLOCK_LOOP; 
	END PROCESS; 
 
	PROCESS   -- Process for CCLK 
		VARIABLE TX_OUT : LINE; 
 
		BEGIN 
		-- -------------------- 
		CE <= transport '0'; 
		CLR <= transport '1'; 
		UP <= transport std_logic_vector'("00"); --0 
		-- -------------------- 
		WAIT FOR 100 ns; -- Time=100 ns 
		CLR <= transport '0'; 
		UP <= transport std_logic_vector'("00"); --0 
		-- -------------------- 
		WAIT FOR 100 ns; -- Time=200 ns 
		CLR <= transport '0'; 
		UP <= transport std_logic_vector'("01"); --1 
		-- -------------------- 
		WAIT FOR 100 ns; -- Time=300 ns 
		UP <= transport std_logic_vector'("01"); --1 
		-- -------------------- 
		WAIT FOR 100 ns; -- Time=400 ns 
		UP <= transport std_logic_vector'("11"); --3 
		-- -------------------- 
		WAIT FOR 100 ns; -- Time=500 ns 
		UP <= transport std_logic_vector'("11"); --3 
		-- -------------------- 
		WAIT FOR 100 ns; -- Time=600 ns 
		UP <= transport std_logic_vector'("10"); --2 
		-- -------------------- 
		WAIT FOR 100 ns; -- Time=700 ns 
		UP <= transport std_logic_vector'("00"); --0 
		-- -------------------- 
		WAIT FOR 100 ns; -- Time=800 ns 
		CLR <= transport '1'; 
		UP <= transport std_logic_vector'("00"); --0 
		-- -------------------- 
		WAIT FOR 120 ns; -- Time=920 ns 
		-- -------------------- 
 
		STD.TEXTIO.write(TX_OUT, string'("Total[]")); 
		STD.TEXTIO.writeline(results, TX_OUT); 
		ASSERT (FALSE) REPORT 
			"Success! Simulation for annotation completed" 
			SEVERITY FAILURE; 
	END PROCESS; 
END testbench_arch; 
 
CONFIGURATION count4_cfg OF countest IS 
	FOR testbench_arch 
	END FOR; 
END count4_cfg;