www.pudn.com > xc9572_1.rar > counter8.vhi

 
-- VHDL Instantiation Created from source file counter8.vhd -- 15:18:03 04/05/2006 
-- 
-- Notes:  
-- 1) This instantiation template has been automatically generated using types 
-- std_logic and std_logic_vector for the ports of the instantiated module 
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit 
 
	COMPONENT counter8 
	PORT( 
		Din : IN std_logic_vector(7 downto 0); 
		CE : IN std_logic; 
		CLR : IN std_logic; 
		UP : IN std_logic; 
		L : IN std_logic; 
		CCLK : IN std_logic;           
		Qout : OUT std_logic_vector(7 downto 0) 
		); 
	END COMPONENT; 
 
	Inst_counter8: counter8 PORT MAP( 
		Din => , 
		CE => , 
		CLR => , 
		UP => , 
		L => , 
		CCLK => , 
		Qout =>  
	);