www.pudn.com > xc9572_1.rar > counter8.syr
Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
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--> Reading design: counter8.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : counter8.prj
Input Format : mixed
Ignore Synthesis Constraint File : NO
Verilog Include Directory :
---- Target Parameters
Output File Name : counter8
Output Format : NGC
Target Device : xc9500
---- Source Options
Top Module Name : counter8
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
Equivalent register Removal : YES
MACRO Preserve : YES
XOR Preserve : YES
---- General Options
Optimization Goal : Area
Optimization Effort : 1
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
lso : counter8.lso
verilog2001 : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file D:/FPGA/TEST/xc_9572/counter8.vhd in Library work.
Entity (Architecture ) compiled.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity (Architecture ).
Entity analyzed. Unit generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit .
Related source file is D:/FPGA/TEST/xc_9572/counter8.vhd.
Found 13-bit updown counter for signal .
Summary:
inferred 1 Counter(s).
Unit synthesized.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 1
13-bit updown counter : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit ...
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : counter8.ngr
Top Level Output File Name : counter8
Output Format : NGC
Optimization Goal : Area
Keep Hierarchy : YES
Target Technology : xc9500
Macro Preserve : YES
XOR Preserve : YES
wysiwyg : NO
Design Statistics
# IOs : 31
Macro Statistics :
# Registers : 13
# 1-bit register : 13
# Xors : 24
# 1-bit xor2 : 24
Cell Usage :
# BELS : 196
# AND2 : 74
# INV : 50
# OR2 : 48
# XOR2 : 24
# FlipFlops/Latches : 13
# FDC : 13
# IO Buffers : 31
# IBUF : 18
# OBUF : 13
=========================================================================
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