www.pudn.com > xc9572_1.rar > count9.vhd

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
--  Uncomment the following lines to use the declarations that are 
--  provided for instantiating Xilinx primitive components. 
--library UNISIM; 
--use UNISIM.VComponents.all; 
 
entity count9 is 
    Port ( CE :  in std_logic; 
           CLR : in std_logic; 
           UP : in std_logic; 
           CCLK : in std_logic; 
           Qout : out std_logic_vector(6 downto 0)); 
end count9; 
 
architecture Behavioral of count9 is 
 signal Temp:std_logic_vector(6 downto 0); 
 begin 
     
	process(CCLK,CLR) 
	 begin 
	 if(CLR='1') then 
	    Temp<=(others=>'0'); 
	 elsif (CCLK'event and CCLK='1') then 
		if(CE='0') then 
		  if(UP='1') then 
		     
			 Temp<= Temp+1; 
		  elsif(UP='0') then 
		   Temp<= Temp-1; 	  
		  end if; 
	   end if; 
	  end if; 
	 end process; 
 	 Qout<=temp; 
 
end Behavioral;