www.pudn.com > xc9572_1.rar > count4_timesim.vhd

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim count4.nga count4_timesim.vhd 
-- Input file    : count4.nga
-- Output file   : count4_timesim.vhd
-- Design name   : count4.nga
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : XC9572-10-TQ100 (Speed File: Version 3.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity count4 is
  port (
    CCLK : in STD_LOGIC := 'X'; 
    CLR : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    UP : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    Qout : out STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end count4;

architecture Structure of count4 is
  signal CCLK_IBUF : STD_LOGIC; 
  signal CLR_IBUF : STD_LOGIC; 
  signal UP_0_IBUF : STD_LOGIC; 
  signal UP_1_IBUF : STD_LOGIC; 
  signal CE_IBUF : STD_LOGIC; 
  signal Temp_0_Q : STD_LOGIC; 
  signal Temp_1_Q : STD_LOGIC; 
  signal Temp_2_Q : STD_LOGIC; 
  signal dir_Q : STD_LOGIC; 
  signal Temp_0_Q_0 : STD_LOGIC; 
  signal Temp_0_D : STD_LOGIC; 
  signal Temp_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal Temp_0_RSTF : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal Temp_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal Temp_0_CLKF : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal Temp_0_D1 : STD_LOGIC; 
  signal Temp_0_D2 : STD_LOGIC; 
  signal Temp_0_D2_PT_0 : STD_LOGIC; 
  signal Temp_0_D2_PT_1 : STD_LOGIC; 
  signal Temp_1_Q_1 : STD_LOGIC; 
  signal Temp_1_D : STD_LOGIC; 
  signal Temp_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal Temp_1_RSTF : STD_LOGIC; 
  signal Temp_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal Temp_1_CLKF : STD_LOGIC; 
  signal Temp_1_D1 : STD_LOGIC; 
  signal Temp_1_D2 : STD_LOGIC; 
  signal Temp_1_D2_PT_0 : STD_LOGIC; 
  signal Temp_1_D2_PT_1 : STD_LOGIC; 
  signal Temp_2_Q_2 : STD_LOGIC; 
  signal Temp_2_D : STD_LOGIC; 
  signal Temp_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal Temp_2_RSTF : STD_LOGIC; 
  signal Temp_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal Temp_2_CLKF : STD_LOGIC; 
  signal Temp_2_D1 : STD_LOGIC; 
  signal Temp_2_D2 : STD_LOGIC; 
  signal Temp_2_D2_PT_0 : STD_LOGIC; 
  signal Temp_2_D2_PT_1 : STD_LOGIC; 
  signal dir_Q_3 : STD_LOGIC; 
  signal dir_FBK : STD_LOGIC; 
  signal dir_D : STD_LOGIC; 
  signal dir_tsimcreated_xor_Q : STD_LOGIC; 
  signal dir_RSTF : STD_LOGIC; 
  signal dir_tsimcreated_prld_Q : STD_LOGIC; 
  signal dir_CLKF : STD_LOGIC; 
  signal dir_D1 : STD_LOGIC; 
  signal dir_D2 : STD_LOGIC; 
  signal dir_D2_PT_0 : STD_LOGIC; 
  signal dir_D2_PT_1 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_0_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_0_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_1_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_1_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_2_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Temp_2_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dir_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dir_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dir_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dir_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dir_D2_PT_1_IN3 : STD_LOGIC; 
  signal Temp : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  CCLK_IBUF_4 : X_BUF
    port map (
      I => CCLK,
      O => CCLK_IBUF
    );
  CLR_IBUF_5 : X_BUF
    port map (
      I => CLR,
      O => CLR_IBUF
    );
  UP_0_IBUF_6 : X_BUF
    port map (
      I => UP(0),
      O => UP_0_IBUF
    );
  UP_1_IBUF_7 : X_BUF
    port map (
      I => UP(1),
      O => UP_1_IBUF
    );
  CE_IBUF_8 : X_BUF
    port map (
      I => CE,
      O => CE_IBUF
    );
  Qout_0_Q : X_BUF
    port map (
      I => Temp_0_Q,
      O => Qout(0)
    );
  Qout_1_Q : X_BUF
    port map (
      I => Temp_1_Q,
      O => Qout(1)
    );
  Qout_2_Q : X_BUF
    port map (
      I => Temp_2_Q,
      O => Qout(2)
    );
  Qout_3_Q : X_BUF
    port map (
      I => dir_Q,
      O => Qout(3)
    );
  Temp_0_Q_9 : X_BUF
    port map (
      I => Temp_0_Q_0,
      O => Temp_0_Q
    );
  Temp_0_Q_10 : X_BUF
    port map (
      I => Temp_0_Q_0,
      O => Temp(0)
    );
  Temp_0_tsimcreated_xor_Q_11 : X_XOR2
    port map (
      I0 => Temp_0_D,
      I1 => Temp_0_Q_0,
      O => Temp_0_tsimcreated_xor_Q
    );
  Temp_0_tsimcreated_prld_Q_12 : X_OR2
    port map (
      I0 => Temp_0_RSTF,
      I1 => PRLD,
      O => Temp_0_tsimcreated_prld_Q
    );
  Temp_0_REG : X_FF
    port map (
      I => Temp_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Temp_0_CLKF,
      SET => Gnd,
      RST => Temp_0_tsimcreated_prld_Q,
      O => Temp_0_Q_0
    );
  Gnd_13 : X_ZERO
    port map (
      O => Gnd
    );
  Vcc_14 : X_ONE
    port map (
      O => Vcc
    );
  Temp_0_D_15 : X_XOR2
    port map (
      I0 => Temp_0_D1,
      I1 => Temp_0_D2,
      O => Temp_0_D
    );
  Temp_0_D1_16 : X_ZERO
    port map (
      O => Temp_0_D1
    );
  Temp_0_D2_PT_0_17 : X_AND3
    port map (
      I0 => UP_0_IBUF,
      I1 => NlwInverterSignal_Temp_0_D2_PT_0_IN1,
      I2 => NlwInverterSignal_Temp_0_D2_PT_0_IN2,
      O => Temp_0_D2_PT_0
    );
  Temp_0_D2_PT_1_18 : X_AND3
    port map (
      I0 => NlwInverterSignal_Temp_0_D2_PT_1_IN0,
      I1 => UP_1_IBUF,
      I2 => NlwInverterSignal_Temp_0_D2_PT_1_IN2,
      O => Temp_0_D2_PT_1
    );
  Temp_0_D2_19 : X_OR2
    port map (
      I0 => Temp_0_D2_PT_0,
      I1 => Temp_0_D2_PT_1,
      O => Temp_0_D2
    );
  Temp_0_CLKF_20 : X_AND2
    port map (
      I0 => CCLK_IBUF,
      I1 => CCLK_IBUF,
      O => Temp_0_CLKF
    );
  Temp_0_RSTF_21 : X_AND2
    port map (
      I0 => CLR_IBUF,
      I1 => CLR_IBUF,
      O => Temp_0_RSTF
    );
  Temp_1_Q_22 : X_BUF
    port map (
      I => Temp_1_Q_1,
      O => Temp_1_Q
    );
  Temp_1_Q_23 : X_BUF
    port map (
      I => Temp_1_Q_1,
      O => Temp(1)
    );
  Temp_1_tsimcreated_xor_Q_24 : X_XOR2
    port map (
      I0 => Temp_1_D,
      I1 => Temp_1_Q_1,
      O => Temp_1_tsimcreated_xor_Q
    );
  Temp_1_tsimcreated_prld_Q_25 : X_OR2
    port map (
      I0 => Temp_1_RSTF,
      I1 => PRLD,
      O => Temp_1_tsimcreated_prld_Q
    );
  Temp_1_REG : X_FF
    port map (
      I => Temp_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Temp_1_CLKF,
      SET => Gnd,
      RST => Temp_1_tsimcreated_prld_Q,
      O => Temp_1_Q_1
    );
  Temp_1_D_26 : X_XOR2
    port map (
      I0 => Temp_1_D1,
      I1 => Temp_1_D2,
      O => Temp_1_D
    );
  Temp_1_D1_27 : X_ZERO
    port map (
      O => Temp_1_D1
    );
  Temp_1_D2_PT_0_28 : X_AND4
    port map (
      I0 => UP_0_IBUF,
      I1 => NlwInverterSignal_Temp_1_D2_PT_0_IN1,
      I2 => NlwInverterSignal_Temp_1_D2_PT_0_IN2,
      I3 => Temp(0),
      O => Temp_1_D2_PT_0
    );
  Temp_1_D2_PT_1_29 : X_AND4
    port map (
      I0 => NlwInverterSignal_Temp_1_D2_PT_1_IN0,
      I1 => UP_1_IBUF,
      I2 => NlwInverterSignal_Temp_1_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Temp_1_D2_PT_1_IN3,
      O => Temp_1_D2_PT_1
    );
  Temp_1_D2_30 : X_OR2
    port map (
      I0 => Temp_1_D2_PT_0,
      I1 => Temp_1_D2_PT_1,
      O => Temp_1_D2
    );
  Temp_1_CLKF_31 : X_AND2
    port map (
      I0 => CCLK_IBUF,
      I1 => CCLK_IBUF,
      O => Temp_1_CLKF
    );
  Temp_1_RSTF_32 : X_AND2
    port map (
      I0 => CLR_IBUF,
      I1 => CLR_IBUF,
      O => Temp_1_RSTF
    );
  Temp_2_Q_33 : X_BUF
    port map (
      I => Temp_2_Q_2,
      O => Temp_2_Q
    );
  Temp_2_tsimcreated_xor_Q_34 : X_XOR2
    port map (
      I0 => Temp_2_D,
      I1 => Temp_2_Q_2,
      O => Temp_2_tsimcreated_xor_Q
    );
  Temp_2_tsimcreated_prld_Q_35 : X_OR2
    port map (
      I0 => Temp_2_RSTF,
      I1 => PRLD,
      O => Temp_2_tsimcreated_prld_Q
    );
  Temp_2_REG : X_FF
    port map (
      I => Temp_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Temp_2_CLKF,
      SET => Gnd,
      RST => Temp_2_tsimcreated_prld_Q,
      O => Temp_2_Q_2
    );
  Temp_2_D_36 : X_XOR2
    port map (
      I0 => Temp_2_D1,
      I1 => Temp_2_D2,
      O => Temp_2_D
    );
  Temp_2_D1_37 : X_ZERO
    port map (
      O => Temp_2_D1
    );
  Temp_2_D2_PT_0_38 : X_AND5
    port map (
      I0 => UP_0_IBUF,
      I1 => NlwInverterSignal_Temp_2_D2_PT_0_IN1,
      I2 => NlwInverterSignal_Temp_2_D2_PT_0_IN2,
      I3 => Temp(0),
      I4 => Temp(1),
      O => Temp_2_D2_PT_0
    );
  Temp_2_D2_PT_1_39 : X_AND5
    port map (
      I0 => NlwInverterSignal_Temp_2_D2_PT_1_IN0,
      I1 => UP_1_IBUF,
      I2 => NlwInverterSignal_Temp_2_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Temp_2_D2_PT_1_IN3,
      I4 => NlwInverterSignal_Temp_2_D2_PT_1_IN4,
      O => Temp_2_D2_PT_1
    );
  Temp_2_D2_40 : X_OR2
    port map (
      I0 => Temp_2_D2_PT_0,
      I1 => Temp_2_D2_PT_1,
      O => Temp_2_D2
    );
  Temp_2_CLKF_41 : X_AND2
    port map (
      I0 => CCLK_IBUF,
      I1 => CCLK_IBUF,
      O => Temp_2_CLKF
    );
  Temp_2_RSTF_42 : X_AND2
    port map (
      I0 => CLR_IBUF,
      I1 => CLR_IBUF,
      O => Temp_2_RSTF
    );
  dir_Q_43 : X_BUF
    port map (
      I => dir_Q_3,
      O => dir_Q
    );
  dir_FBK_44 : X_BUF
    port map (
      I => dir_Q_3,
      O => dir_FBK
    );
  dir_tsimcreated_xor_Q_45 : X_XOR2
    port map (
      I0 => dir_D,
      I1 => dir_Q_3,
      O => dir_tsimcreated_xor_Q
    );
  dir_tsimcreated_prld_Q_46 : X_OR2
    port map (
      I0 => dir_RSTF,
      I1 => PRLD,
      O => dir_tsimcreated_prld_Q
    );
  dir_REG : X_FF
    port map (
      I => dir_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => dir_CLKF,
      SET => Gnd,
      RST => dir_tsimcreated_prld_Q,
      O => dir_Q_3
    );
  dir_D_47 : X_XOR2
    port map (
      I0 => dir_D1,
      I1 => dir_D2,
      O => dir_D
    );
  dir_D1_48 : X_ZERO
    port map (
      O => dir_D1
    );
  dir_D2_PT_0_49 : X_AND4
    port map (
      I0 => UP_0_IBUF,
      I1 => NlwInverterSignal_dir_D2_PT_0_IN1,
      I2 => NlwInverterSignal_dir_D2_PT_0_IN2,
      I3 => dir_FBK,
      O => dir_D2_PT_0
    );
  dir_D2_PT_1_50 : X_AND4
    port map (
      I0 => NlwInverterSignal_dir_D2_PT_1_IN0,
      I1 => UP_1_IBUF,
      I2 => NlwInverterSignal_dir_D2_PT_1_IN2,
      I3 => NlwInverterSignal_dir_D2_PT_1_IN3,
      O => dir_D2_PT_1
    );
  dir_D2_51 : X_OR2
    port map (
      I0 => dir_D2_PT_0,
      I1 => dir_D2_PT_1,
      O => dir_D2
    );
  dir_CLKF_52 : X_AND2
    port map (
      I0 => CCLK_IBUF,
      I1 => CCLK_IBUF,
      O => dir_CLKF
    );
  dir_RSTF_53 : X_AND2
    port map (
      I0 => CLR_IBUF,
      I1 => CLR_IBUF,
      O => dir_RSTF
    );
  NlwInverterBlock_Temp_0_D2_PT_0_IN1 : X_INV
    port map (
      I => UP_1_IBUF,
      O => NlwInverterSignal_Temp_0_D2_PT_0_IN1
    );
  NlwInverterBlock_Temp_0_D2_PT_0_IN2 : X_INV
    port map (
      I => CE_IBUF,
      O => NlwInverterSignal_Temp_0_D2_PT_0_IN2
    );
  NlwInverterBlock_Temp_0_D2_PT_1_IN0 : X_INV
    port map (
      I => UP_0_IBUF,
      O => NlwInverterSignal_Temp_0_D2_PT_1_IN0
    );
  NlwInverterBlock_Temp_0_D2_PT_1_IN2 : X_INV
    port map (
      I => CE_IBUF,
      O => NlwInverterSignal_Temp_0_D2_PT_1_IN2
    );
  NlwInverterBlock_Temp_1_D2_PT_0_IN1 : X_INV
    port map (
      I => UP_1_IBUF,
      O => NlwInverterSignal_Temp_1_D2_PT_0_IN1
    );
  NlwInverterBlock_Temp_1_D2_PT_0_IN2 : X_INV
    port map (
      I => CE_IBUF,
      O => NlwInverterSignal_Temp_1_D2_PT_0_IN2
    );
  NlwInverterBlock_Temp_1_D2_PT_1_IN0 : X_INV
    port map (
      I => UP_0_IBUF,
      O => NlwInverterSignal_Temp_1_D2_PT_1_IN0
    );
  NlwInverterBlock_Temp_1_D2_PT_1_IN2 : X_INV
    port map (
      I => CE_IBUF,
      O => NlwInverterSignal_Temp_1_D2_PT_1_IN2
    );
  NlwInverterBlock_Temp_1_D2_PT_1_IN3 : X_INV
    port map (
      I => Temp(0),
      O => NlwInverterSignal_Temp_1_D2_PT_1_IN3
    );
  NlwInverterBlock_Temp_2_D2_PT_0_IN1 : X_INV
    port map (
      I => UP_1_IBUF,
      O => NlwInverterSignal_Temp_2_D2_PT_0_IN1
    );
  NlwInverterBlock_Temp_2_D2_PT_0_IN2 : X_INV
    port map (
      I => CE_IBUF,
      O => NlwInverterSignal_Temp_2_D2_PT_0_IN2
    );
  NlwInverterBlock_Temp_2_D2_PT_1_IN0 : X_INV
    port map (
      I => UP_0_IBUF,
      O => NlwInverterSignal_Temp_2_D2_PT_1_IN0
    );
  NlwInverterBlock_Temp_2_D2_PT_1_IN2 : X_INV
    port map (
      I => CE_IBUF,
      O => NlwInverterSignal_Temp_2_D2_PT_1_IN2
    );
  NlwInverterBlock_Temp_2_D2_PT_1_IN3 : X_INV
    port map (
      I => Temp(0),
      O => NlwInverterSignal_Temp_2_D2_PT_1_IN3
    );
  NlwInverterBlock_Temp_2_D2_PT_1_IN4 : X_INV
    port map (
      I => Temp(1),
      O => NlwInverterSignal_Temp_2_D2_PT_1_IN4
    );
  NlwInverterBlock_dir_D2_PT_0_IN1 : X_INV
    port map (
      I => UP_1_IBUF,
      O => NlwInverterSignal_dir_D2_PT_0_IN1
    );
  NlwInverterBlock_dir_D2_PT_0_IN2 : X_INV
    port map (
      I => CE_IBUF,
      O => NlwInverterSignal_dir_D2_PT_0_IN2
    );
  NlwInverterBlock_dir_D2_PT_1_IN0 : X_INV
    port map (
      I => UP_0_IBUF,
      O => NlwInverterSignal_dir_D2_PT_1_IN0
    );
  NlwInverterBlock_dir_D2_PT_1_IN2 : X_INV
    port map (
      I => CE_IBUF,
      O => NlwInverterSignal_dir_D2_PT_1_IN2
    );
  NlwInverterBlock_dir_D2_PT_1_IN3 : X_INV
    port map (
      I => dir_FBK,
      O => NlwInverterSignal_dir_D2_PT_1_IN3
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => PRLD);

end Structure;