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-- Copyright (c) 1995-2003 Xilinx, Inc. 
-- All Right Reserved. 
-------------------------------------------------------------------------------- 
--   ____  ____  
--  /   /\/   /  
-- /___/  \  /    Vendor: Xilinx  
-- \   \   \/     Version : 6.3i 
--  \   \         Application :  
--  /   /         Filename : xil_2596_5 
-- /___/   /\     Timestamp : 04/04/2006 16:47:25 
-- \   \  /  \  
--  \___\/\___\  
-- 
--Command:  
--Design Name: copy_of_cb8ce 
-- 
 
library ieee; 
use ieee.std_logic_1164.ALL; 
use ieee.numeric_std.ALL; 
-- synopsys translate_off 
library UNISIM; 
use UNISIM.Vcomponents.ALL; 
-- synopsys translate_on 
 
entity copy_of_cb8ce is 
   port ( C   : in    std_logic;  
          CE  : in    std_logic;  
          CLR : in    std_logic;  
          CEO : out   std_logic;  
          Q   : out   std_logic_vector (7 downto 0);  
          TC  : out   std_logic); 
end copy_of_cb8ce; 
 
architecture BEHAVIORAL of copy_of_cb8ce is 
begin 
end BEHAVIORAL; 
 
-- synopsys translate_off 
configuration CFG_copy_of_cb8ce of  copy_of_cb8ce is 
   for BEHAVIORAL 
   end for; 
end CFG_copy_of_cb8ce; 
-- synopsys translate_on