www.pudn.com > g729Decoder.rar > Lpc_lsp.asm


;========================================================================== 
;  File Name 
;  ---------- 
;  LPC_LSP.ASM 
; 
;  Brief Description of the Code: 
;  ------------------------------ 
;  Compute the LSPs from  the LPC coefficients  (order=10) 
; 
;  Ref 
;  ------ 
;  LPC.C 
;========================================================================== 
 
;------------------------------------------------------------- 
;  procedure Az_lsp: 
;            ~~~~~~ 
;  Compute the LSPs from  the LPC coefficients  (order=10) 
;------------------------------------------------------------- 
; int lpc_lsp( 
;   Word16 a[],        /* (i) Q12 : predictor coefficients              */ 
;   Word16 lsp[],      /* (o) Q15 : line spectral pairs                 */ 
;   Word16 old_lsp[]   /* (i)     : old lsp[] (in case not found 10 roots) */ 
; ) 
;------------------------------------------------------------- 
;  Input : 
;        Constants : 
;                  Addr_lpc_coefQ12 = &a[1] 
;                  Addr_lsp_coef = lsp 
; 
;  Output: 
;        If successfully find 10 lsp 
;            A = 0, and Addr_lsp_coef = lsp 
;        else 
;            A = 1 
; 
;  Modified : DP, AR0, AR1, AR2, AR3, AR4, AR5, AR6 
;-------------------------------------------------------------- 
		 
        .MMREGS 
 
        .include ..\include\const.h 
        .include ..\include\lpc_lsp.h 
 
        .text 
        .ref	 Addr_lpc_coefQ12 
        .ref     Addr_lsp_coef 
        .ref     Grid 
 
        .def     lpc_lsp 
        .ref     Chebps_11 
        .ref     Chebps_10 
        .bss     Overflow,1,0,0 
        .global  pChebps 
        .bss     pChebps,1,0,0 
 
One_Q10         .set     1024 
One_Q11         .set     2048 
One_Q14         .set     16383 
 
        .asg    "AR1", pLspCoef 
        .asg    "AR2", pGrid 
        .asg    "AR3", pf 
        .asg    "AR4", pXlow 
        .asg    "AR4", pXmid 
 
lpc_lsp: 
        STM     #f1, AR2 
        STM     #f2, AR3 
        ST      #Chebps_11,*(pChebps) 
 
        ST        #0,*(Overflow) 
 
        STM     #Addr_lpc_coefQ12, AR4 
        STM     #Addr_lpc_coefQ12+M-1, AR5 
 
        LD      #One_Q11, 16, B            ; B = f1[0] = f2[0] = 1.0 
        ADD     *AR4, *AR5, A              ; f1[1] = a[1] + a[M] - f1[0] 
        LD      A, -1, A 
        SUB     B, A 
        STL     A, -16, *AR2 
 
        SUB     *AR4+, *AR5-, A            ; f1[2] = a[1] - a[M] + f1[0] 
        LD      A, -1, A 
        ADD     B, A 
        STL     A, -16, *AR3 
 
        STM     #NC-2, BRC 
        RPTB    Init_Blk_End1 - 1 
        ADD     *AR4, *AR5, A              ; f1[i+1] = a[i+1] + a[M-i] - f1[i] 
        LD      A, -1, A 
        SUB     *AR2+, 16, A 
        LD      A, -16, A 
        CALL    #CheckOverFlow 
        STL     A, *AR2 
 
        SUB     *AR4+, *AR5-, A            ; f2[i+1] = a[i+1] + a[M-i] - f2[i] 
        LD      A, -1, A 
        ADD     *AR3+, 16, A 
        LD      A, -16, A 
        CALL    #CheckOverFlow 
        STL     A, *AR3 
 
Init_Blk_End1 
        LD      *(Overflow), B 
        BC      #Bzero, BEQ 
 
        STM     #f1, AR2 
        STM     #f2, AR3 
 
        STM     #Addr_lpc_coefQ12, AR4 
        STM     #Addr_lpc_coefQ12+M-1, AR5 
 
        ST      #Chebps_10,*(pChebps) 
        LD      #One_Q10, 16, B            ; B = f1[0] = f2[0] = 1.0 
        ADD     *AR4, *AR5, A              ; f1[1] = a[1] + a[M] - f1[0] 
        LD      A, -2, A 
        SUB     B, A 
        STL     A, -16, *AR2 
 
        SUB     *AR4+, *AR5-, A            ; f1[2] = a[1] - a[M] + f1[0] 
        LD      A, -2, A 
        ADD     B, A 
        STL     A, -16, *AR3 
 
        STM     #NC-2, BRC 
        RPTB    Init_Blk_End - 1 
        ADD     *AR4, *AR5, A              ; f1[i+1] = a[i+1] + a[M-i] - f1[i] 
        LD      A, -2, A 
        SUB     *AR2+, 16, A 
        STL     A, -16, *AR2 
 
        SUB     *AR4+, *AR5-, A            ; f2[i+1] = a[i+1] + a[M-i] - f2[i] 
        LD      A, -2, A 
        ADD     *AR3+, 16, A 
        STL     A, -16, *AR3 
Bzero: 
 
Init_Blk_End 
        LD      #Addr_Lpc_Lsp_Buf, DP 
        STM     #5, BK 
        STM     #1, AR0 
        STM     #Addr_lsp_coef, AR1 
        STM     #Grid, AR2 
        STM     #f1, AR3 
        STM     #xlow, AR4 
 
        MVDD    *pGrid+, *pXlow             ; xlow = grid[0] 
;        CALLD   Chebps_11                   ; AR4 -> xlow, AR3 -> f[] 
        LD      *(pChebps), B 
        CALAD   B                   ; AR4 -> xlow, AR3 -> f[] 
        STM     #NC-3, BRC 
        SAT     A 
        STL     A, -16, ylow                     ; ylow = (*pChebps)(xlow,coef,NC) 
 
Outter_Loop 
           MVDK    *pXlow+, xhigh           ; xhigh = xlow 
           MVDK    *pXlow-, yhigh           ; yhigh = ylow 
           MVDD    *pGrid+, *pXlow          ; xlow  = grid[j] 
        LD      *(pChebps), B 
        CALAD   B                   ; AR4 -> xlow, AR3 -> f[] 
;           CALLD   Chebps_11 
           STM     #NC-3, BRC 
           SAT     A 
           MPYA    yhigh 
           BCD     Outter_Loop_Test, BGT 
           STL     A, -16, ylow                  ; ylow = (*pChebps)(xlow,coef,NC) 
           NOP 
                                            ; divide 4 times the interval 
           STM     #2-1,AR6 
           STM     #xmid, AR4 
Inner_Loop 
                 LD     xhigh, -1, A 
 
                 ADD    xlow,  -1, A 
                 STL     A, *pXmid 
 
		        LD      *(pChebps), B 
    		    CALAD   B                   ; AR4 -> xlow, AR3 -> f[] 
                STM     #NC-3, BRC 
                SAT     A 
                MPYA    ylow                ; A = ymid, B = sign 
                STM     #xhigh, AR5 
                XC      2, BGT 
                        STM     #xlow,  AR5 ; AR5 -> x 
 
                MVDD    *pXmid, *AR5+       ; AR5 -> y 
                BANZD   Inner_Loop, *AR6- 
                STL     A, -16, *AR5 
 
Inner_Loop_End 
; "STM  #xlow, AR4" is moved behind "BCD  Store_Lsp, BEQ" for efficiency 
; Linear interpolation : xint = xlow - ylow*(xhigh-xlow)/(yhigh-ylow) 
 
           LD      yhigh, 16, B 
           SUB     ylow,  16, B             ; B = yhigh - ylow 
           LD      *pXlow, A 
           BCD     Store_Lsp, BEQ 
           STM     #xlow, AR4 
 
           LD      xhigh, 16, A 
           SUB     xlow,  16, A 
           STL     A, -16, x                     ; x = xhigh - xlow 
           ABS     B, A 
           EXP     A 
           STM     #AL, AR5 
           NORM    A 
           STL     A, -16, y 
 
           LDM     T, A 
           SUB     #20-16, A 
           LD      *AR5, ASM 
 
           LD      #One_Q14, 16, A 
           RPT     #16-2 
	             SUBC    y, A 
 
           STLM    A, T 
           MPY     x, A 
           LD      A, ASM, A 
           SFTA        A,-16,A 
           LD          A,15,A 
           LD          A,1,A 
 
           XC      1, BLT 
                   NEG     A                ; A = t0 
           MPYA    ylow 
           LD      *pXlow, A 
           LD      B, -11, B 
           SUB     B, A 
 
           ; ----------------------- 
 
Store_Lsp 
           STL     A, *pLspCoef+            ; A = xint 
           STL     A, *pXlow 
 
           LDM     AR3, A                   ; if   AR3 == f1 then AR3 = f2 
           XOR     #f1, A                   ; else AR3 =  f1 
           XOR     #f2, A 
           STLM    A, AR3 
 
;           CALLD    Chebps_11 
        LD      *(pChebps), B 
        CALAD   B                   ; AR4 -> xlow, AR3 -> f[] 
           STM     #NC-3, BRC 
           SAT     A 
           STL     A, -16, ylow 
 
Outter_Loop_Test 
           CMPM    *pGrid, 1 
           LDM     pLspCoef, A 
           SUB     #Addr_lsp_coef + M, A 
           BC      Outter_Loop, NTC, NC 
 
        XOR     A, A 
        XC      1, NC 
                LD      #1, A 
        RET 
 
CheckOverFlow: 
         LD        A, B 
         SUB       #32767,B,B 
         BC        L4,BLEQ 
 
         LD        #32767, A 
         ST        #1,*(Overflow) 
         B         L6 
 
L4: 
         LD        A, B 
         SUB       #-32768,B,B 
         BC        L6,BGEQ 
 
         ST        #1,*(Overflow) 
         LD        #-32768, A 
 
L6: 
         RET