www.pudn.com > RS485_USART-ok.rar > speed.h, change:2007-09-29,size:3492b


//*---------------------------------------------------------------------------- 
//*      Shenzhen ANCHE Tech CO.,LTD 
//*---------------------------------------------------------------------------- 
//*---------------------------------------------------------------------------- 
//* File Name         : speed.h 
//* Designer            : Tianlong Jing, at 2006 
//* Object              : led Library. 
//* 
//* 1.0 25/08/00 LLD    : Creation 
//* 2.0 10/12/01 PFi    : Access to Data Pointer/Counter Registers has been removed. 
//*                     : The RevA of the M558000 does not features DAC PDC. 
//*---------------------------------------------------------------------------- 
#ifndef __SPEED_H 
#define __SPEED_H 
 
#include "includes.h" 
 
//与TC相关的宏定义(Page 34) 
#define TC_CLKS_MCK2             0x0  	//timer clock1 
#define TC_CLKS_MCK8             0x1  	//timer clock2 
#define TC_CLKS_MCK32           0x2  	//timer clock3 
#define TC_CLKS_MCK128         0x3  	//timer clock4 
#define TC_CLKS_MCK1024     	0x4  	//timer clock5 
 
#define TC_CLKS_XC0              	0x5  //XC0 
#define TC_CLKS_XC1              	0x6  //XC1 
#define TC_CLKS_XC2              	0x7  //XC2 
 
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------  
// this is defined in ioat91sam7x256.h 
/* 
#define	AT91C_TC_COVFS		0x1 << 0		// Counter Overflow 
#define	AT91C_TC_LOVRS		0x1 << 1		// Load Overrun 
#define	AT91C_TC_CPAS			0x1 << 2		// RA Compare 
#define	AT91C_TC_CPBS			0x1 << 3		// RB Compare 
#define	AT91C_TC_CPCS			0x1 << 4		// RC compare 
#define	AT91C_TC_LDRAS		0x1 << 5		// RA Loading 
#define	AT91C_TC_LDRBS		0x1 << 6		// RB Loading 
#define	AT91C_TC_ETRGS		0x1 << 7		// External Trigger 
#define	AT91C_TC_CLKSTA		0x1 << 16	// Clock Enable 
#define	AT91C_TC_MTIOA		0x1 << 17	// TIOA Mirror 
#define	AT91C_TC_MTIOB		0x1 << 18	// TIOB Mirror */ 
 
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------  
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------  
 
//#define 	SPEED_CAP_FIFO_BUF_SIZE	16 
#define 	SPEED_CAP_FIFO_BUF_SIZE	5 
 
//#define   SPEED_CAP_PERIOD_MAX_REMOVE		1			// 去掉1个最长周期 
//#define	SPEED_CAP_PERIOD_MIN_REMOVE			5			// 去掉最小的5个短周期 
#define   SPEED_CAP_PERIOD_MAX_REMOVE		0			// 去掉1个最长周期 
#define	SPEED_CAP_PERIOD_MIN_REMOVE			0			// 去掉最小的5个短周期 
 
// 0 --- lowest ; 7 --- highest 
// the PIT interrupt level is 0 (lowest) 
#define SPEED_CAP0_INTERRUPT_LEVEL	 	AT91C_AIC_PRIOR_HIGHEST - 1 
#define SPEED_CAP2_INTERRUPT_LEVEL	 	AT91C_AIC_PRIOR_HIGHEST - 2 
#define FRAME_NUM  2 
#define FIRST  0 
#define SECOND  1 
 
 
typedef struct struct_Pluse_Cap 
{ 
	INT16U	overflow;	// Counter Overflow times, the max overflow is 0x7fff 
	INT16U	capture;		// RA Loading value 
}STRUCT_PLUSE_CAP; 
 
typedef struct Speed_CAP_fifo 
{ 
       INT16U TC_Capt[2]; 
	STRUCT_PLUSE_CAP cap[SPEED_CAP_FIFO_BUF_SIZE];		// FIFO 缓冲区 
	INT8U	ptr;						// FIFO 指针 
	//INT32U	sum;					// 当前缓冲区和 
	//INT32U	width;					// 当前缓冲区平脉冲宽度 
}SPEED_CAP_FIFO; 
 
void Speed_Init(void); 
//void Speed_Coef_Set(STRUCT_NVS_PARA *conf); 
 
//void Speed_CAP0_Interrupt_Handler(void); 
//void Speed_CAP2_Interrupt_Handler(void); 
void Speed_1st_IRQ_Handle(AT91PS_TC pTC); 
void Speed_2nd_IRQ_Handle(AT91PS_TC pTC); 
 
//void Speed_Read(float *speed_l, float *speed_r); 
INT32U freq_1st_Read(void); 
INT32U freq_2nd_Read(void); 
 
#endif /* __SPEED_H */