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/**************************************************/   
/*               EMIFA and EMIFB                  */ 
/**************************************************/ 
#define EMIFA_GCTL       0x01800000 
#define EMIFA_CE1        0x01800004 
#define EMIFA_CE0        0x01800008 
#define EMIFA_CE2        0x01800010 
#define EMIFA_CE3        0x01800014 
#define EMIFA_SDRAMCTL   0x01800018 
#define EMIFA_SDRAMREF   0x0180001c 
#define EMIFA_SDRAMEXT   0x01800020 
#define EMIFA_CE1SECCTL  0x01800044 
#define EMIFA_CE0SECCTL  0x01800048 
#define EMIFA_CE2SECCTL  0x01800050 
#define EMIFA_CE3SECCTL  0x01800054 
 
#define EMIFB_GCTL       0x01A80000 
#define EMIFB_CE1        0x01A80004 
#define EMIFB_CE0        0x01A80008 
#define EMIFB_CE2        0x01A80010 
#define EMIFB_CE3        0x01A80014 
#define EMIFB_SDRAMCTL   0x01A80018 
#define EMIFB_SDRAMREF   0x01A8001c 
#define EMIFB_SDRAMEXT   0x01A80020 
#define EMIFB_CE1SECCTL  0x01A80044 
#define EMIFB_CE0SECCTL  0x01A80048 
#define EMIFB_CE2SECCTL  0x01A80050 
#define EMIFB_CE3SECCTL  0x01A80054 
/**************************************************/   
/*                 INT                            */ 
/**************************************************/ 
#define MUXH             0x019C0000 
#define MUXL             0x019C0004 
#define EXTPOL           0x019C0008 
/**************************************************/   
/*                  GPIO                          */ 
/**************************************************/ 
#define GPEN             0x01B00000 
#define GPDIR            0x01B00004 
#define GPVAL            0x01B00008 
#define GPDH             0x01B00010 
#define GPHM             0x01B00014 
#define GPDL             0x01B00018 
#define GPLM             0x01B0001c 
#define GPGC             0x01B00020 
#define GPPOL            0x01B00024 
/**************************************************/   
/*                  TIMER0,1,2                    */ 
/**************************************************/ 
#define TIMER0_CTL       0x01940000 
#define TIMER0_PRD       0x01940004 
#define TIMER0_CNT       0x01940008 
 
#define TIMER1_CTL       0x01980000 
#define TIMER1_PRD       0x01980004 
#define TIMER1_CNT       0x01980008 
/**************************************************/   
/*       EDMA and Channel 2,4,6,7,N,Null          */ 
/**************************************************/ 
#define EPRH             0x01A0FF9C 
#define CIPRH            0x01A0FFA4      
#define CIERH            0x01A0FFA8      
#define CCERH            0x01A0FFAC      
#define ERH              0x01A0FFB0 
#define EERH             0x01A0FFB4 
#define ECRH             0x01A0FFB8 
#define ESRH             0x01A0FFBC 
#define PQAR0            0x01A0FFC0 
#define PQAR1            0x01A0FFC4 
#define PQAR2            0x01A0FFC8 
#define PQAR3            0x01A0FFCC 
#define EPRL             0x01A0FFDC 
#define PQSR             0x01A0FFE0 
#define CIPRL            0x01A0FFE4 
#define CIERL            0x01A0FFE8 
#define CCERL            0x01A0FFEC 
#define ERL              0x01A0FFF0 
#define EERL             0x01A0FFF4 
#define ECRL             0x01A0FFF8 
#define ESRL             0x01A0FFFC 
 
#define EDMA2_OPT        0x01A00030 //TIMER1 
#define EDMA2_SRC        0x01A00034 
#define EDMA2_FR_ELCNT   0x01A00038 
#define EDMA2_DST        0x01A0003C 
#define EDMA2_FR_ELIDX   0x01A00040 
#define EDMA2_EL_LINK    0x01A00044 
 
#define EDMA4_OPT        0x01A00060//GPIO4/EX_INT4 
#define EDMA4_SRC        0x01A00064 
#define EDMA4_FR_ELCNT   0x01A00068 
#define EDMA4_DST        0x01A0006C 
#define EDMA4_FR_ELIDX   0x01A00070 
#define EDMA4_EL_LINK    0x01A00074 
 
#define EDMA6_OPT        0x01A00090//GPIO6/EX_INT6 
#define EDMA6_SRC        0x01A00094 
#define EDMA6_FR_ELCNT   0x01A00098 
#define EDMA6_DST        0x01A0009C 
#define EDMA6_FR_ELIDX   0x01A000A0 
#define EDMA6_EL_LINK    0x01A000A4 
 
#define EDMA7_OPT        0x01A000A8//GPIO7/EX_INT7 
#define EDMA7_SRC        0x01A000AC 
#define EDMA7_FR_ELCNT   0x01A000B0 
#define EDMA7_DST        0x01A000B4 
#define EDMA7_FR_ELIDX   0x01A000B8 
#define EDMA7_EL_LINK    0x01A000BC 
 
#define EDMA8_OPT        0x01A000C0//GPIO0 
#define EDMA8_SRC        0x01A000C4 
#define EDMA8_FR_ELCNT   0x01A000C8 
#define EDMA8_DST        0x01A000CC 
#define EDMA8_FR_ELIDX   0x01A000D0 
#define EDMA8_EL_LINK    0x01A000D4 
 
#define LINKN_OPT        0x01A00600//Reload/LinkN 
#define LINKN_SRC        0x01A00604 
#define LINKN_FR_ELCNT   0x01A00608 
#define LINKN_DST        0x01A0060C 
#define LINKN_FR_ELIDX   0x01A00610 
#define LINKN_EL_LINK    0x01A00614 
 
 
#define NULL_OPT        0x01A00618//Reload NULL_LINGKM 
#define NULL_SRC        0x01A0061C 
#define NULL_FR_ELCNT   0x01A00620 
#define NULL_DST        0x01A00624 
#define NULL_FR_ELIDX   0x01A00628 
#define NULL_EL_LINK    0x01A0062C 
 
#define QDMA_S_OPT      0x02000020 //QDMA 
#define QDMA_SRC        0x02000004  
#define QDMA_CNT        0x02000008 
#define QDMA_DST        0x0200000C 
#define QDMA_IDX        0x02000010 
 
#define DP_FLG          0xB0010000  
 
#define CCFG            0x01840000 //L2 CACHE MODE 
/******************    END    ************************/