www.pudn.com > Dm642_Encoder.rar > Boot_Load.asm

        .title  "Flash bootup utility for 6416" 
        
; EMIFB registers and values    
EMIF_GCTL 	  .equ    0x01A80000  ;EMIFB global control      
EMIF_CE1      .equ    0x01A80004  ;address of EMIF CE1 control reg.  
EMIF_CE0      .equ    0x01A80008  ;EMIFB CE0control           
EMIF_SDCTRL   .equ    0x01A80018  ;EMIFB SDRAM control      
EMIF_SDRP     .equ    0x01A8001c  ;EMIFB SDRM refresh period  
EMIF_CE1_8    .equ    0xffffff03  ;EMIFB CE1 space parameter 
EMIF_GCTL_V	  .equ    0x000827d4  ;EMIFB global control value 
EMIF_CE0_V    .equ    0xffffff03  ;EMIFB CE0control   ;0x30 
EMIF_SDCTRL_V .equ    0x07117000  ;EMIFB SDRAM control ;0x73380000     
 
; QDMA registers and values 
QDMA_OPT	  .equ	  0x02000020  ;QDMA options register 
QDMA_OPT_VAL  .equ	  0x21200001  ;QDMA options ;0x21280001 
QDMA_SRC	  .equ	  0x02000004  ;QDMA source address register 
QDMA_CNT	  .equ	  0x02000008  ;QDMA count register 
QDMA_DST	  .equ	  0x0200000c  ;QDMA destination address register 
QDMA_S_IDX	  .equ	  0x02000010  ;QDMA index pseudo-register 
 
  
 .sect ".boot"  
 .global _boot 
; .ref _c_int00  
  
_boot:              
                                            
; **************        
; Configure EMIF                 
; ************** 
                             
            mvkl  EMIF_GCTL,A4    ;EMIF_GCR address ->A4 
      ||    mvkl  EMIF_GCTL_V,B4       
 
            mvkh  EMIF_GCTL,A4 
      ||    mvkh  EMIF_GCTL_V,B4   
                             
            stw   B4,*A4              
 
            mvkl  EMIF_CE1,A4      ;EMIF_CE1 address ->A4 
      ||    mvkl  EMIF_CE1_8,B4    ; 
 
            mvkh  EMIF_CE1,A4 
      ||    mvkh  EMIF_CE1_8,B4 
       
            stw   B4,*A4 
     
 
; *************             
; Copy Sections 
; ************* 
 
 
	    	mvkl  copyTable, a3	; load table pointer 
	    	mvkh  copyTable, a3 
	    	 
copy_section_top:	 
	    	ldw   *a3++, b0 ; byte count 
	    	ldw   *a3++, a4	; load ram start address 
	    	ldw   *a3++, b4	; load flash start address 
	    	nop   2 
	[!b0]   b copy_done		; have we copied all sections?  
	    	nop 5 
	    	 
; copy this section with QDMA 
 
			mvkl  QDMA_OPT,A5	; set QDMA options 
 	||		mvkl  QDMA_OPT_VAL,B5       
 			mvkh  QDMA_OPT,A5 
 	||		mvkh  QDMA_OPT_VAL,B5 
 			stw   B5,*A5 
 			mvkl  QDMA_SRC,A5	; load source address 
 			mvkh  QDMA_SRC,A5       
 			stw   B4,*A5	         
			shr   B0,2,B1      	; divide size by 4 (because we're in 32-bit mode) 
			mvkl  QDMA_CNT,A5 	; load word count 
			mvkh  QDMA_CNT,A5       
 			stw   B1,*A5             
 			mvkl  QDMA_DST,A5	; load destination address 
 			mvkh  QDMA_DST,A5       
 			stw   A4,*A5	   
			mvkl  QDMA_S_IDX,A5 ; set index. writing to this register will 
 			mvkh  QDMA_S_IDX,A5 ; also initiate the transfer. 
 			zero  B5 
 			stw   B5,*A5        ; go! 
 
; next section	            
 
			b	  copy_section_top 
			nop   5 
 
copy_done:  ; done with section copying.   
			; jump to _c_int00 
			 
		;	mvkl .S2 _c_int00, B0 
        ;   mvkh .S2 _c_int00, B0 
            mvkl .S2 0x2c00, B0 
            mvkh .S2 0x0000, B0 
            B    .S2 B0 
            nop   5 
                
                
; *************             
; Section Table 
; ************* 
                
                
    ;; Table of sections to copy. Format is: 
    ;; word 0:	byte count 
    ;; word 1:	run address 
    ;; word 2:	load address 
     
;   .ref textSize,   textRun ; these symbols created with 
;   .ref biosSize,   biosRun ; linker command file 
;   .ref trcinitSize,trcinitRun 
;   .ref hwi_vecRun 
    
copyTable: 
 
	;; .vec 
    .word 0x00000260  
    .word 0x00000400 
    .word 0x64000400 
            
    ;; .text 
    .word 0x00002660 
    .word 0x00000660 
    .word 0x64000660    
     
    ;; .cinit 
    .word 0x0000010c 
    .word 0x00002cc0 
    .word 0x64002cc0 
    ;; end of table 
    .word 0 
    .word 0 
    .word 0