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// megafunction wizard: %LPM_RAM_DP+% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: RAM2.v // Megafunction Name(s): // altsyncram // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 5.0 Build 148 04/26/2005 SJ Full Version // ************************************************************ //Copyright (C) 1991-2005 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module RAM2 ( data_a, wren_a, address_a, data_b, address_b, wren_b, clock_a, clock_b, q_a, q_b); input [7:0] data_a; input wren_a; input [9:0] address_a; input [7:0] data_b; input [9:0] address_b; input wren_b; input clock_a; input clock_b; output [7:0] q_a; output [7:0] q_b; wire [7:0] sub_wire0; wire [7:0] sub_wire1; wire [7:0] q_a = sub_wire0[7:0]; wire [7:0] q_b = sub_wire1[7:0]; altsyncram altsyncram_component ( .wren_a (wren_a), .clock0 (clock_a), .wren_b (wren_b), .clock1 (clock_b), .address_a (address_a), .address_b (address_b), .data_a (data_a), .data_b (data_b), .q_a (sub_wire0), .q_b (sub_wire1) // synopsys translate_off , .aclr0 (), .aclr1 (), .addressstall_a (), .addressstall_b (), .byteena_a (), .byteena_b (), .clocken0 (), .clocken1 (), .rden_b () // synopsys translate_on ); defparam altsyncram_component.intended_device_family = "Cyclone II", altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", altsyncram_component.width_a = 8, altsyncram_component.widthad_a = 10, altsyncram_component.numwords_a = 1024, altsyncram_component.width_b = 8, altsyncram_component.widthad_b = 10, altsyncram_component.numwords_b = 1024, altsyncram_component.lpm_type = "altsyncram", altsyncram_component.width_byteena_a = 1, altsyncram_component.width_byteena_b = 1, altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.indata_reg_b = "CLOCK1", altsyncram_component.address_reg_b = "CLOCK1", altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1", altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.clock_enable_input_b = "BYPASS", altsyncram_component.clock_enable_output_b = "BYPASS", altsyncram_component.power_up_uninitialized = "FALSE"; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" // Retrieval info: PRIVATE: VarWidth NUMERIC "1" // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" // Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: Clock NUMERIC "5" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: Clock_A NUMERIC "0" // Retrieval info: PRIVATE: Clock_B NUMERIC "0" // Retrieval info: PRIVATE: REGdata NUMERIC "1" // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" // Retrieval info: PRIVATE: REGwren NUMERIC "1" // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" // Retrieval info: PRIVATE: REGrren NUMERIC "0" // Retrieval info: PRIVATE: REGq NUMERIC "0" // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" // Retrieval info: PRIVATE: CLRdata NUMERIC "0" // Retrieval info: PRIVATE: CLRwren NUMERIC "0" // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" // Retrieval info: PRIVATE: CLRrren NUMERIC "0" // Retrieval info: PRIVATE: CLRq NUMERIC "0" // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: enable NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" // Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0] // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a // Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0] // Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0] // Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL address_a[9..0] // Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0] // Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL address_b[9..0] // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b // Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a // Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b // Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 // Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 // Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 // Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0 // Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 // Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0 // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 // Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL RAM2.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM2.inc TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM2.cmp TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM2.bsf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM2_inst.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM2_bb.v TRUE