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FL C:/vga_new300/vgashow/uartrec.vhd 2004/06/11.14:25:02 
FL D:/vgashow/uartrec.vhd 2004/06/06.11:30:16 
FL D:/vgashow/wrlogo.vhd 2004/06/06.14:07:12 
FL C:/vga_new300/vgashow/vga.vhd 2004/06/11.14:25:02 
FL D:/vgashow/vga.vhd 2004/06/06.11:30:42 
FL G:/doc/lab6/wrlogo.vhd 2004/06/11.14:25:02 
FL E:/FPGA/Exp6-VGA/vga.vhd 2004/06/11.14:25:02 
EN work/VGA             FL E:/FPGA/Exp6-VGA/vga.vhd PB ieee/STD_LOGIC_1164 \ 
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED 
AR work/VGA/BEHAVIORAL  FL E:/FPGA/Exp6-VGA/vga.vhd EN work/VGA 
FL E:/FPGA/Exp6-VGA/uartrec.vhd 2004/06/11.14:25:02 
EN work/UARTREC         FL E:/FPGA/Exp6-VGA/uartrec.vhd PB ieee/STD_LOGIC_1164 \ 
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED 
AR work/UARTREC/BEHAVIORAL FL E:/FPGA/Exp6-VGA/uartrec.vhd EN work/UARTREC \ 
      CP IBUF           CP BUFG 
FL C:/vga_new300/vgashow/top.vhd 2004/06/11.14:25:02 
FL G:/doc/lab6/vga.vhd 2004/06/11.14:25:02 
FL D:/vgashow/top.vhd 2004/06/06.14:10:00 
FL E:/FPGA/Exp6-VGA/wrlogo.vhd 2004/06/11.14:25:02 
EN work/WRLOGO          FL E:/FPGA/Exp6-VGA/wrlogo.vhd PB ieee/STD_LOGIC_1164 \ 
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED 
AR work/WRLOGO/BEHAVIORAL FL E:/FPGA/Exp6-VGA/wrlogo.vhd EN work/WRLOGO CP LOGO 
FL D:/vgashow/wrground.vhd 2004/06/06.11:59:42 
EN work/WRGROUND        FL D:/vgashow/wrground.vhd PB ieee/STD_LOGIC_1164 \ 
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED 
AR work/WRGROUND/BEHAVIORAL FL D:/vgashow/wrground.vhd EN work/WRGROUND CP GROUND 
FL E:/FPGA/Exp6-VGA/top.vhd 2004/06/11.14:25:02 
EN work/TOP             FL E:/FPGA/Exp6-VGA/top.vhd PB ieee/STD_LOGIC_1164 \ 
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED 
AR work/TOP/BEHAVIORAL  FL E:/FPGA/Exp6-VGA/top.vhd EN work/TOP CP UARTREC \ 
      CP WRLOGO         CP VGA 
FL G:/doc/lab6/uartrec.vhd 2004/06/11.14:25:02 
FL G:/doc/lab6/top.vhd 2004/06/11.14:25:02 
FL C:/vga_new300/vgashow/wrlogo.vhd 2004/06/11.14:25:02