www.pudn.com > Exp6-VGA.rar > vgashow.npl

JDF G 
// Created by Project Navigator ver 1.0 
PROJECT vgashow 
DESIGN vgashow 
DEVFAM virtex2 
DEVFAMTIME 1029737549 
DEVICE xc2v1000 
DEVICETIME 1029737549 
DEVPKG fg456 
DEVPKGTIME 0 
DEVSPEED -4 
DEVSPEEDTIME 1029737549 
DEVTOPLEVELMODULETYPE HDL 
TOPLEVELMODULETYPETIME 0 
DEVSYNTHESISTOOL XST (VHDL/Verilog) 
SYNTHESISTOOLTIME 0 
DEVSIMULATOR Other 
SIMULATORTIME 0 
DEVGENERATEDSIMULATIONMODEL VHDL 
GENERATEDSIMULATIONMODELTIME 0 
SOURCE wrlogo.vhd 
SOURCE uartrec.vhd 
SOURCE ground.xco 
SOURCE wrground.vhd 
SOURCE top.vhd 
SOURCE logo.xco 
SOURCE vga.vhd 
DEPASSOC top top.ucf 
[Normal] 
p_impactConfigMode=xstvhd, spartan2e, Implementation.t_impactProgrammingTool, 1086525977, Boundary Scan 
xilxBitgStart_Clk=xstvhd, spartan2e, Implementation.t_bitFile, 1086935266, JTAG Clock 
[STATUS-ALL] 
top.ngcFile=WARNINGS,1151033666 
top.ngdFile=WARNINGS,1151033716 
[STRATEGY-LIST] 
Normal=True